The appropriate power diodes and low ESR electrolytic cap will have an ESR*C time constant of <10~100us while cheap e-caps rated for much lower ripple current (or no rating given) have higher ESR will be 200uS to >1000us.

So it is not instantaneous but fast. Lower ESR caps are always preferred due to I^2*ESR heat loss.

Meanwhile the load R * C time constant must be chosen for a reasonable ripple level such as 10% where it works out that RC must be>= 16/f for line frequency at bridge input. This results in very large peak currents at full load equal to % Vripple in duty cycle (d) and 1/d in peak charge currents.

Also,with at no load the caps will rise to 1.4*Vac rms at full load and also rise another 8~10% from Vac drop at rated load or in other words the Vdc can swing as much as 50% higher with no compared to full load.

There may be other formulas which determine Load R to Cap ESR ratios, but the C value must only sag 10% at 2f pulse rates for 10% full load ripple.

This is only 1/6th of the exponent RC time constant value slew time for a 60% decay in voltage hence 6T min is needed for 100Hz and 12T for for 50Hz. The bridge is a frequency doubler. The extra storage time to 16T is due approximation errors, voltage margin and cap value aging.

This is why we call it an unregulated power supply.

The appropriate power diodes and low ESR electrolytic cap will have an ESR*C time constant of <10~100us while cheap e-caps rated for much lower ripple current (or no rating given) have higher ESR will be 200uS to >1000us.

So it is not instantaneous but fast. Lower ESR caps are always preferred due to I^2*ESR heat loss.

Meanwhile the load R * C time constant must be chosen for a reasonable ripple level such as 10% where it works out that RC must be>= 16/f for line frequency at bridge input. This results in very large peak currents at full load equal to % Vripple in duty cycle (d) and 1/d in peak charge currents.

Also,with at no load the caps will rise to 1.4*Vac rms at full load and also rise another 8~10% from Vac drop at rated load or in other words the Vdc can swing as much as 50% higher with no compared to full load.

There may be other formulas which determine Load R to Cap ESR ratios, but the C value must only sag 10% at 2f pulse rates for 10% full load ripple.

This is only 1/6th of the exponent RC time constant value slew time for a 60% decay in voltage hence 6T min is needed for 100Hz and 12T for for 50Hz. The bridge is a frequency doubler. The extra storage time to 16T is due approximation errors, voltage margin and cap value aging.

This is why we call it an unregulated power supply.

You can simulate your AC source peak voltage and f, add ESR to the cap with a fixed R and scope the results here.

The appropriate power diodes and low ESR electrolytic cap will have an ESR*C time constant of <10~100us while cheap e-caps rated for much lower ripple current and higher ESR will be 200uS to >1000us.

So it is not instantaneous but fast. Lower ESR caps are always preferred due to I^2 R heat loss.

Meanwhile the load R * C time constant must be chosen for a reasonable ripple level such as 10% where it works out that RC must be>= 16/f for line frequency at bridge input. This results in very large peak currents at full load equal to % Vripple in duty cycle (d) and 1/d in peak charge currents.

Also,with at no load the caps will rise to 1.4*Vac rms at full load and also rise another 8~10% from Vac drop at rated load or in other words the Vdc can swing as much as 50% higher with no compared to full load.

This is why we call it an unregulated power supply.

The appropriate power diodes and low ESR electrolytic cap will have an ESR*C time constant of <10~100us while cheap e-caps rated for much lower ripple current (or no rating given) have higher ESR will be 200uS to >1000us.

So it is not instantaneous but fast. Lower ESR caps are always preferred due to I^2*ESR heat loss.

Meanwhile the load R * C time constant must be chosen for a reasonable ripple level such as 10% where it works out that RC must be>= 16/f for line frequency at bridge input. This results in very large peak currents at full load equal to % Vripple in duty cycle (d) and 1/d in peak charge currents.

Also,with at no load the caps will rise to 1.4*Vac rms at full load and also rise another 8~10% from Vac drop at rated load or in other words the Vdc can swing as much as 50% higher with no compared to full load.

There may be other formulas which determine Load R to Cap ESR ratios, but the C value must only sag 10% at 2f pulse rates for 10% full load ripple.

This is only 1/6th of the exponent RC time constant value slew time for a 60% decay in voltage hence 6T min is needed for 100Hz and 12T for for 50Hz. The bridge is a frequency doubler. The extra storage time to 16T is due approximation errors, voltage margin and cap value aging.

This is why we call it an unregulated power supply.