Timeline for Is it logical to use pull-up resistor on SPI Clock line
Current License: CC BY-SA 3.0
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| when toggle format | what | by | license | comment | |
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| Nov 5, 2016 at 21:43 | comment | added | Majenko | So... don't have it floating then. If you're that concerned about power consumption you won't be floating your pins anyway. | |
| Nov 5, 2016 at 21:42 | comment | added | dim | Except that, if the SPI clock is floating, the logic level sensed at the slave may toggle constantly. And, whatever the state of CS, most likely the input stage of CLK within the slave chip is kept powered on. So this may have unwanted side effects, like excessive power consumption, even if it doesn't affect the chip functionality. | |
| Nov 5, 2016 at 11:32 | history | answered | Majenko | CC BY-SA 3.0 |