For mixed signal designs, layout and placement is generally far more critical than the specific decouplers used, although manufacturers will often state a decoupling scheme if they believe it to be critical.

The rule of thumb (as already noted) is 100nF per power pin and a bulk decoupler for larger components (such as processors, microcontrollers, large FPGAs).

Xilinx goes into quite some detail on this subject.

For mixed signal designs, layout and placement is generally far more critical than the specific decouplers used, although manufacturers will often state a decoupling scheme if they believe it to be critical.

The rule of thumb (as already noted) is 100nF per power pin and a bulk decoupler for larger components (such as processors, microcontrollers, large FPGAs).

Xilinx goes into quite some detail on this subject.