Timeline for Why Data Recovery Block needs to operate at 16 times the baud rate [duplicate]
Current License: CC BY-SA 3.0
11 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Dec 5, 2016 at 12:00 | history | closed |
CL. Dave Tweed |
Duplicate of UART receiver clock speed | |
| S Dec 5, 2016 at 9:49 | history | suggested | Adam Calvet Bohl | CC BY-SA 3.0 |
Tag suggestion and small edits
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| Dec 5, 2016 at 9:49 | answer | added | Andy aka | timeline score: 3 | |
| Dec 5, 2016 at 9:01 | review | Close votes | |||
| Dec 5, 2016 at 12:00 | |||||
| Dec 5, 2016 at 7:51 | review | Suggested edits | |||
| S Dec 5, 2016 at 9:49 | |||||
| Dec 5, 2016 at 7:41 | answer | added | Spehro 'speff' Pefhany | timeline score: 4 | |
| Dec 5, 2016 at 7:27 | comment | added | D.A.S. | The data clock is synchronized to 8 of 16 clock cycles after leading edge of the start bit for asynchronous operation. | |
| Dec 5, 2016 at 7:24 | comment | added | seetharaman | If you know that I intend to hit you with a brick would you be alert/observant? | |
| Dec 5, 2016 at 7:01 | comment | added | Ignacio Vazquez-Abrams | So that it can get enough samples to recover the transmit clock. | |
| Dec 5, 2016 at 7:01 | review | First posts | |||
| Dec 5, 2016 at 11:15 | |||||
| Dec 5, 2016 at 7:00 | history | asked | Prasad Pachu | CC BY-SA 3.0 |