Timeline for Hold Time Violations with Shift Registers/Ring Counters
Current License: CC BY-SA 3.0
7 events
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Feb 20, 2017 at 23:00 | vote | accept | divB | ||
Feb 20, 2017 at 20:53 | comment | added | RoyC | Usually it is tech dependent my experience is with ASIC and there we always use clock trees. If there are hold time violations the tools put in buffers between stages to slow things down a bit. To reiterate if your flops have low or zero hold time use a clock tree. | |
Feb 20, 2017 at 20:48 | comment | added | divB | Great! I had the clock tree first but then I was told I should run the clock opposite of the data and I ran into problems. Before I confirm your answer as solution, to make sure: Running the clock backwards to data is true for shift registers but NOT when there are loops (LSFR, ring counter)? | |
Feb 20, 2017 at 11:16 | history | edited | RoyC | CC BY-SA 3.0 |
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Feb 20, 2017 at 11:03 | history | edited | RoyC | CC BY-SA 3.0 |
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Feb 20, 2017 at 10:57 | history | edited | RoyC | CC BY-SA 3.0 |
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Feb 20, 2017 at 10:50 | history | answered | RoyC | CC BY-SA 3.0 |