Timeline for P-channel MOSFET inrush current limiting
Current License: CC BY-SA 4.0
19 events
| when toggle format | what | by | license | comment | |
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| Feb 29 at 21:58 | history | edited | ocrdu | CC BY-SA 4.0 |
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| Feb 29 at 21:52 | answer | added | Kuba hasn't forgotten Monica | timeline score: 3 | |
| Feb 29 at 21:29 | comment | added | Kuba hasn't forgotten Monica | You can buy current-limiting power switches a dime each pretty much. They'll provide the best performance per dollar. I'd say you won't find the circuits because no one would actually put something like that made from scratch in a product, unless the product was for a hobby or other funky market where price wasn't a concern and the volume was low. | |
| Apr 2, 2021 at 6:06 | answer | added | KarlKarlsom | timeline score: 3 | |
| Dec 21, 2017 at 2:53 | answer | added | Scott | timeline score: 3 | |
| Dec 13, 2017 at 14:51 | answer | added | Olin Lathrop | timeline score: 10 | |
| Dec 13, 2017 at 13:23 | answer | added | Ray Ackley | timeline score: 3 | |
| Oct 4, 2017 at 14:16 | comment | added | DerStrom8 | I did all of my simulations in LTSpice and that was the problem - real world circuits behaved VERY differently. | |
| Oct 4, 2017 at 14:04 | comment | added | Sajeev Ranasinghe | I simulated this a few ways in LTSpice and I don't get as good results from source to gate. Drain to gate I get a good linear controlled response. It's P-channel so I have a BJT pulling the divider at the gate LOW to turn it ON. I used a 10k and 1k divider, and a load of 5 ohms, 5V input, 5uF cap, and the inrush does not overshoot, the ramp is linear at about 6mS for Gate-Drain, and 2mS for D-S, but much nicer looking for Gate-Drain. I think you will get the needed negative feedback from Gate-Drain but not Gate-Source. Anyway - doesn't help with your specific problem, but interesting. | |
| Oct 3, 2017 at 1:41 | comment | added | DerStrom8 | MOSFETs require a voltage differential between the gate and source to switch on. Placing the capacitor on the drain side is far less reliable | |
| Oct 3, 2017 at 1:26 | comment | added | DerStrom8 | @SajeevRanasinghe both are common but placing it between the gate and source is preferred for this application due to the fact that it is on the supply side of the transistor. I tried both methods, but neither worked. I eventually abandoned this idea of current limiting altogether. | |
| Oct 2, 2017 at 14:05 | comment | added | Sajeev Ranasinghe | I believe your capacitor needs to be between gate to drain, not gate to source. Here is an example: mosaic-industries.com/embedded-systems/microcontroller-projects/… | |
| Mar 22, 2017 at 16:34 | comment | added | DerStrom8 | That was my original plan but alas, there do not seem to be any small, SMD NTCs that meet my requirements. They are also a bit unpredictable | |
| Mar 22, 2017 at 14:48 | history | tweeted | twitter.com/StackElectronix/status/844561504825413633 | ||
| Mar 22, 2017 at 13:21 | answer | added | bobflux | timeline score: 4 | |
| Mar 22, 2017 at 13:19 | comment | added | Rohat Kılıç | If the space wasn't an issue then I would say "NTC". sigh! | |
| Mar 22, 2017 at 12:59 | history | edited | DerStrom8 | CC BY-SA 3.0 |
added 26 characters in body
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| Mar 22, 2017 at 12:57 | answer | added | KyranF | timeline score: 3 | |
| Mar 22, 2017 at 12:34 | history | asked | DerStrom8 | CC BY-SA 3.0 |