Timeline for What is the best abstraction for HDL code?
Current License: CC BY-SA 3.0
6 events
| when toggle format | what | by | license | comment | |
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| Apr 13, 2012 at 16:00 | answer | added | Brian Carlton | timeline score: 3 | |
| Apr 13, 2012 at 15:06 | comment | added | darron | As far as I can tell, the only way to ensure your HDL is synthesizable is to follow known patterns. There are supposedly a few good books you might look for. I lurked on the comp.arch.fpga and comp.lang.vhdl groups for a long time absorbing information. IMHO, gate level is ridiculous for anything complex. I would suggest that you embrace the higher level modeling, just learn a few good patterns (all synchronous unless you have a very good reason not to, careful attention to clock domains, a good state machine model you use consistently, etc) | |
| Apr 13, 2012 at 15:05 | answer | added | user3624 | timeline score: 8 | |
| Apr 13, 2012 at 14:51 | history | tweeted | twitter.com/#!/StackElectronix/status/190814454815010816 | ||
| Apr 13, 2012 at 13:31 | comment | added | clabacchio | I think there is no best way; one is better suited for fitting the behavior, while one is closer to the HW implementation, so will map more directly the real configuration | |
| Apr 13, 2012 at 13:29 | history | asked | Rick_2047 | CC BY-SA 3.0 |