Skip to main content
Electrical Engineering

Return to Answer

deleted 75 characters in body
Source Link
clabacchio
clabacchio
  • 13.6k
  • 4
  • 45
  • 80

Probably this solution is more easily implemented in VHDL, but,

If you can settle for pseudo-random numbers (which is, they change all the time but the sequence is repeatable from a given starting point), you can go for a shift register-based pseudo random generator (link on the image):

enter image description here

See also this alternative page

You can extend it to the number of bits that you require at the output, but make sure that the XOR "scrambles" the bits so as it doesn't fall into a loop with a limited number of different output sequences.

Here there is a tool to generate CRC (Cyclic Redundancy Code?) in VHDL and Verilog, and it's also discussed here

Probably this solution is more easily implemented in VHDL, but,

If you can settle for pseudo-random numbers (which is, they change all the time but the sequence is repeatable from a given starting point), you can go for a shift register-based pseudo random generator (link on the image):

enter image description here

See also this alternative page

You can extend it to the number of bits that you require at the output, but make sure that the XOR "scrambles" the bits so as it doesn't fall into a loop with a limited number of different output sequences.

Here there is a tool to generate CRC (Cyclic Redundancy Code?) in VHDL and Verilog, and it's also discussed here

If you can settle for pseudo-random numbers (which is, they change all the time but the sequence is repeatable from a given starting point), you can go for a shift register-based pseudo random generator (link on the image):

enter image description here

See also this alternative page

You can extend it to the number of bits that you require at the output, but make sure that the XOR "scrambles" the bits so as it doesn't fall into a loop with a limited number of different output sequences.

Here there is a tool to generate CRC (Cyclic Redundancy Code?) in VHDL and Verilog, and it's also discussed here

added 11 characters in body
Source Link
clabacchio
clabacchio
  • 13.6k
  • 4
  • 45
  • 80

Probably this solution is more easily implemented in VHDL, but, ifProbably this solution is more easily implemented in VHDL, but,

If you can settle for pseudo-random numbers (which is, they change all the time but the sequence is repeatable from a given starting point), you can go for a shift register-based pseudo random generator (link on the image):

enter image description here

See also this alternative page

You can extend it to the number of bits that you require at the output, but make sure that the XOR "scrambles" the bits so as it doesn't fall into a loop with a limited number of different output sequences.

Here there is a tool to generate CRC (Cyclic Redundancy Code?) in VHDL and Verilog, and it's also discussed here

Probably this solution is more easily implemented in VHDL, but, if you can settle for pseudo-random numbers (which is, they change all the time but the sequence is repeatable from a given starting point), you can go for a shift register-based pseudo random generator (link on the image):

enter image description here

See also this alternative page

You can extend it to the number of bits that you require at the output, but make sure that the XOR "scrambles" the bits so as it doesn't fall into a loop with a limited number of different output sequences.

Probably this solution is more easily implemented in VHDL, but,

If you can settle for pseudo-random numbers (which is, they change all the time but the sequence is repeatable from a given starting point), you can go for a shift register-based pseudo random generator (link on the image):

enter image description here

See also this alternative page

You can extend it to the number of bits that you require at the output, but make sure that the XOR "scrambles" the bits so as it doesn't fall into a loop with a limited number of different output sequences.

Here there is a tool to generate CRC (Cyclic Redundancy Code?) in VHDL and Verilog, and it's also discussed here

Source Link
clabacchio
clabacchio
  • 13.6k
  • 4
  • 45
  • 80

Probably this solution is more easily implemented in VHDL, but, if you can settle for pseudo-random numbers (which is, they change all the time but the sequence is repeatable from a given starting point), you can go for a shift register-based pseudo random generator (link on the image):

enter image description here

See also this alternative page

You can extend it to the number of bits that you require at the output, but make sure that the XOR "scrambles" the bits so as it doesn't fall into a loop with a limited number of different output sequences.