Timeline for Random bit sequence using Verilog

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when toggle format	what		by	license	comment
Jun 11, 2020 at 15:10	history	edited	CommunityBot		Commonmark migration
Apr 24, 2012 at 15:54	comment	added	The Photon		@NeelMehta, the basic reason is that HDLs (Verilog and VHDL) were not invented for the purpose of designing logic, but for modeling logic that already exists. Why we use it for designing logic instead of the original purpose is a whole new question. But functions like $random let you model logic at a higher level, in terms of behavior, instead of the detailed level that is needed for synthesis.
Apr 24, 2012 at 15:52	comment	added	The Photon		@FedericoRusso, Yes, "not synthesizable" means the synthesis tool will not be able to generate corresponding logic in the physical FPGA. You could, however, for example, use this function in a testbench to generate a stimulus when you simulate a design you are working on.
Apr 24, 2012 at 9:56	comment	added	Neel Mehta		I agree with Federico. Why have something which is non-synthesizable?
Apr 24, 2012 at 8:15	comment	added	Federico Russo		@ThePhoton: not synthesizable, does that mean you can't create FPGA code from it? What's the use then?
Apr 23, 2012 at 19:09	comment	added	The Photon		@NeelMehta, FYI, BrianCarlton's answer answers the question you asked, but will not be synthesizable.
Apr 23, 2012 at 17:39	history	answered	Brian Carlton	CC BY-SA 3.0