Timeline for Random bit sequence using Verilog
Current License: CC BY-SA 4.0
5 events
| when toggle format | what | by | license | comment | |
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| Nov 17, 2019 at 17:05 | comment | added | The Photon | @Alexis_FR_JP, thanks, fixed. | |
| Nov 17, 2019 at 17:04 | history | edited | The Photon | CC BY-SA 4.0 |
edited body
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| Nov 17, 2019 at 10:05 | comment | added | None |
For 5bits. d <= { d[3:0], d[4] ^ d[3] }; is wrong, it should be 2 and 4 (xapp052)
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| Apr 24, 2012 at 11:39 | vote | accept | Neel Mehta | ||
| Apr 24, 2012 at 2:12 | history | answered | The Photon | CC BY-SA 3.0 |