Timeline for Eagle component went to bottom layer but should be on top
Current License: CC BY-SA 3.0
6 events
| when toggle format | what | by | license | comment | |
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| May 30, 2017 at 0:02 | comment | added | DavidCyr2000 | Anonymous: There must be polygons defined for the FET to sit on for cooling. One polygon also covers the 4 drain pins that are common. Another polygon covers the 3 common source pins. DRC complains there is overlap, but I assumed that was an acceptable error since the objective is correct. Maybe Eagle is preventing a connection on the top layer because the polygon does not have the same net name as the pins, which would also explain the OVERLAP error. This is a test to show a much simplified version of the problem. So, traces will be wide, two-sided with lots of vias, 3 oz. copper, etc. | |
| May 29, 2017 at 21:53 | comment | added | Anonymous | @ChrisStratton Because actual device's pads are covered by the polygons/rectangles drawn at the package level in library editor. Most probably source package used was DPACK. | |
| May 29, 2017 at 21:11 | comment | added | Chris Stratton | @Anonymous that fails to explain why the one visible air wire matches the extremely consistent endpoint of each trace in the wrong place on the wrong side of the board. Clearly the tool wants to connect them in those places; the question is why. | |
| May 29, 2017 at 21:00 | comment | added | Anonymous | @DaveTweed C3 airwire was manually routed wire before, then was deleted, but the shape remains. | |
| May 29, 2017 at 20:06 | comment | added | Dave Tweed | No, something else is wrong. The airwires are not even going to the centers of the "pads" -- note the one at the top connected to C3. Something is really messed up here, but I can't imagine what it might be. | |
| May 29, 2017 at 19:00 | history | answered | kva | CC BY-SA 3.0 |