Timeline for Eagle configure autorouter to solder components (except vias) only on bottom layer of double sided PCB
Current License: CC BY-SA 3.0
5 events
| when toggle format | what | by | license | comment | |
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| Jun 19, 2017 at 19:43 | comment | added | Tom Carpenter |
The downside is you then get errors from overlapping copper. A better approach would be to draw a box (4 lines) around each pin on the tRestrict layer. That will indicate to the autorouter not to put any copper going through the tRestrict lines, and won't cause DRC errors as long as your lines don't overlap the pins.
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| Jun 19, 2017 at 18:02 | history | edited | Marwan Nabil | CC BY-SA 3.0 |
edited body
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| Jun 16, 2017 at 19:33 | review | Late answers | |||
| Jun 16, 2017 at 21:28 | |||||
| Jun 16, 2017 at 19:18 | review | First posts | |||
| Jun 16, 2017 at 19:27 | |||||
| Jun 16, 2017 at 19:17 | history | answered | Marwan Nabil | CC BY-SA 3.0 |