Timeline for VHDL process requires multiple clock cycles
Current License: CC BY-SA 3.0
7 events
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| Jun 25, 2017 at 20:33 | comment | added | Dave Tweed |
By the time you get that diagram fully implemented, you'll have additional logic to handle unconditional/conditional absolute/relative branches (and subroutine call/return? But I see no paths to transfer the PC to/from memory). In any case, it makes even less sense to have a separate bus dedicated to PCNext alone.
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| Jun 25, 2017 at 19:55 | comment | added | Liam F-A | I completely agree, but our teacher gave us a list of signals that we had to use. I guess he wants us to recreate this diagram using VHDL | |
| Jun 25, 2017 at 18:42 | comment | added | Dave Tweed |
In that case, why have PCNext at all? Just updatePC the same way you do cycle -- i.e., PC <= std_logic_vector(unsigned(PC) + 4);
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| Jun 25, 2017 at 14:35 | comment | added | Liam F-A |
Thanks @Dave ! I'd use this answer, only the requirements of this project say that I have to code the PC in a process
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| Jun 25, 2017 at 13:30 | history | edited | Dave Tweed | CC BY-SA 3.0 |
Add second paragraph
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| Jun 25, 2017 at 11:18 | history | edited | Dave Tweed | CC BY-SA 3.0 |
fix typo
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| Jun 25, 2017 at 11:07 | history | answered | Dave Tweed | CC BY-SA 3.0 |