Timeline for SDRAM Prototype vs Production Woes
Current License: CC BY-SA 3.0
13 events
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| May 15, 2012 at 13:34 | comment | added | Mike DeSimone | Where does SSTL come into this? When I had SDRAM, it just needed 3.3V LVTTL. No 50 ohm lines, no RT, just RS. James, 75 ohm is fine for single-ended signals; the key is not to change it along the length of the trace. | |
| May 14, 2012 at 22:02 | comment | added | James | Hello @TonyStewart, thanks for your support. 1) Prototype board did not require fast slew. Enabled with no change in effect. 2) Unsure what this means - clock is an output? 3) Hysteresis was left enabled. Disabled with no change in effect. 4) Increased slew not enabled on proto. Enabled with no change in effect. 5) Not tested. 7) Pin Config function does not alter other bits. 8) Discrete code for control pins, for loop for data/address 9) When do I need to enable WE? EMC controller should do this for me? 10) Bits are NOTed before being set. I have another prototype on order, be here next week. | |
| May 14, 2012 at 14:33 | history | edited | D.A.S. | CC BY-SA 3.0 |
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| May 14, 2012 at 12:13 | comment | added | James | Also - your example gives 50Ohm impedance for the transmission line. I have read that for this the transmission line width should be half the dialectric height (for microstrip). This results in wider trace that I can fit in my routing. I have got most lines to 78Ohm impedance. The via's are 74Ohm impedance so I belive I little reflection problems because of this. | |
| May 14, 2012 at 12:11 | comment | added | James | Hi Leon, I have looked at hiring a scope, comes out at £500 for a week. This is for a 1Ghz Lecroy scope, so I may go for that to try and figure this out. I do not use any termination scheme on the address lines. I belived those ones you have referenced are for DDR ram? I do have some pull ups on the CONTROL lines, these are in the middle (length) of the transmission line (33k). | |
| May 14, 2012 at 10:40 | comment | added | Leon Heller | If you don't possess a suitable scope, perhaps you should hire one for a week or two. | |
| May 14, 2012 at 9:55 | history | edited | D.A.S. | CC BY-SA 3.0 |
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| May 12, 2012 at 19:18 | comment | added | James | I did not pay for impedance control on these boards. The simulated lines in Hyperlynx (MentorGraphics) showed pretty much perfect (or well within spec) waveforms based on my routed design. To model this I recreated each transmission line and via along with IBIS models. I do not have a scope of sufficient bandwidth the properly investigate the actual signals =( | |
| May 11, 2012 at 20:59 | comment | added | D.A.S. | generally for low complexity Qty 100 PWB's I would not pay for ICT (test), but these have blind tracks so I would ... something to consider... and measure the capacitance on a bare board V+<> GND | |
| May 11, 2012 at 20:31 | comment | added | ajs410 | While wiring a trace (press W in PCB view), press the Tab key and you will see the estimated impedance. | |
| May 11, 2012 at 18:57 | comment | added | dext0rb | Just a comment for OP - I see OP is using Altium Designer, and there is an impedance calculator built into the software. I haven't used it much but I know its there somewhere! | |
| May 11, 2012 at 18:34 | history | edited | D.A.S. | CC BY-SA 3.0 |
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| May 11, 2012 at 18:29 | history | answered | D.A.S. | CC BY-SA 3.0 |