Timeline for How is it possible that lower CAS latency and lower timings on RAM memory to result in lower performance?
Current License: CC BY-SA 3.0
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| Aug 15, 2017 at 21:43 | comment | added | user16324 | Also, sometimes you find as you lower the clock period, you need to increase a delay to meet a memory's timing requirements (published in its datasheet) - e.g. if Trc must be >= 40ns that's a CAS delay of 1 clock cycle at a 40ns (25MHz) clock, but 2 cycles ( 60ns) at a 30ns (33MHz) clock, so the faster clock reduces that aspect of performance. So study the memory's datasheet to find its limitations. | |
| Aug 15, 2017 at 21:14 | comment | added | user16324 | No, ECC memory has nothing to do with improving performance, but detects memory errors in stored data (e.g. from background radiation). | |
| Aug 15, 2017 at 21:05 | history | asked | yoyo_fun | CC BY-SA 3.0 |