Timeline for DDR threshold levels and timing constraints
Current License: CC BY-SA 3.0
4 events
| when toggle format | what | by | license | comment | |
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| Feb 17, 2020 at 10:09 | comment | added | Russell McMahon♦ | Related to your deleted "How to do voltage shifting of a RETURN TO ZERO signal?" question. PLEASE do no delete questions when people have started to put effort into helping you. ALL we need is for you to make your question clear and we can very probably help. You want output as 4 levels (+/-2, +/- 14 BUT R1 has only 3 levels - so cannot be directly translated. - a diagram of what you want would be extremely helpful. | |
| Sep 2, 2017 at 19:20 | comment | added | user39551 | This is not from datasheet , it is from application note AN2582 from freescale. It just mentioned over there and they havent defiend what is AC & DC parameters? Is it something related to biasing or small signal analysis? | |
| Sep 2, 2017 at 17:18 | comment | added | Peter Smith | The datasheets from Micron (which is what this looks like) are extremely detailed. What part of the datasheet information are you having trouble with? | |
| Sep 2, 2017 at 11:22 | history | asked | user39551 | CC BY-SA 3.0 |