Timeline for Gilbert-Cell Operating Point
Current License: CC BY-SA 3.0
12 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Oct 4, 2017 at 10:33 | vote | accept | Max | ||
| Oct 2, 2017 at 16:26 | comment | added | user16324 | @glen_geek - right, forgot about the NE602. Confirms the problem though! | |
| Oct 2, 2017 at 14:46 | comment | added | glen_geek | @BrianDrummond The popular NE602 Gilbert Cell runs with +6V Vcc. Like the OP's scenario, its top collectors are biased only 0.6v below Vcc. Not much headroom, and its IP3 sucks, because its internal biasing is meant for low-current use. | |
| Oct 2, 2017 at 14:42 | answer | added | glen_geek | timeline score: 1 | |
| Oct 2, 2017 at 10:54 | comment | added | Max | Ok: we need 0.7V (Ube) at the node Ldeg. Just because to ensure that the transistor can work properly. This means that we need a base voltage at T5 of minimum 0.7V. The collector node voltage of T5 must then be higher than the base node voltage of T5. Now: is there a restriction for Ubc or must it be just higher than the base node voltage? | |
| Oct 2, 2017 at 10:33 | comment | added | user16324 | Haven't seen many Gilbert cells lately ... when the classic MC1495 came out, 12V or 15V would be a better guess for VCC, which may affect things. | |
| Oct 2, 2017 at 9:32 | comment | added | Bimpelrekkie | Collector node voltage of T1 is 4.6V. Why? You're still not getting it. You start at the top but that is not the right way. Start at the bottom, the current mirror. How low can we take the collector voltage of the mirror output? That's the node with \$L_{deg}\$. That also limits the base voltage of T5. Then how low can we take the collector of T5? That is set by the base voltage of T1,T2. | |
| Oct 2, 2017 at 9:14 | comment | added | Max | Ok, back: Collector node voltage of T1 is 4.6V. My problem is that I dont know what base node voltage I have to set up for T1. It must be definitely smaller than 4.6V but it shouldn't be to small, as it determines Uce=Ucb+Ube. So, if it is to small, Uce is to high and there is to much current. If the base node voltage is to high, the transistor will change its mode to saturation? But what will be the optimum node Voltage for T1,T5, respectively? Is it 0.7V below the collector node voltage? | |
| Oct 2, 2017 at 9:03 | comment | added | Bimpelrekkie | You now base your reasoning on an assumption that VB,T1 = 4V. You can do that but it might not give an optimum solution. For T5 you have to the same as for T1,T2, so what happens when VB,T5 is too low/high, what would be a good choice for T5? Then when you know that, go up to T1,T2. Note that the base voltage and emitter voltage for a transistor are linked (Vbe = 0.7V) but the collector voltage is not, it is determined "from above". | |
| Oct 2, 2017 at 8:57 | comment | added | Max | Well, I have to bias T5 independently from T1, right? What I have to check is: if the base node Voltage of T1 is for example 4V, we have a collector node voltage at T5 of ~4V-0.7V=3.3V. Therefore I need to set up the base node voltage of T5 to a value lower than 3.3 V: But how much lower? | |
| Oct 2, 2017 at 8:51 | comment | added | Bimpelrekkie | Look at the schematic, imagine what happens if the voltage at that DC-biasing point (base of T1, T2) is too low or too high. What happens then? If you make the voltage very high that would limit the possible voltage swing at the output (collectors of T1, T2). If the voltage is too low what will happen to T5? The resistors in the blue part of the schematic are chosen such that there is a good compromise between these effects. | |
| Oct 2, 2017 at 8:33 | history | asked | Max | CC BY-SA 3.0 |