Timeline for VHDL D-type asynch flip flop
Current License: CC BY-SA 3.0
8 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Oct 19, 2017 at 4:29 | answer | added | Blair Fonville | timeline score: 3 | |
| Oct 19, 2017 at 2:18 | answer | added | matryx | timeline score: 1 | |
| Oct 8, 2017 at 18:56 | comment | added | super95 | is there a way of doing this with creating a second process? | |
| Oct 8, 2017 at 18:49 | comment | added | Claudio Avi Chami | The way to do this is to create a top block who instantiates two instances of a component. The component instantiated is the D- flip flop you created. Search for components and entities on VHDL | |
| Oct 8, 2017 at 18:26 | comment | added | sarthak | You can have multiple entities in same file. | |
| Oct 8, 2017 at 18:24 | comment | added | super95 | what do you mean another entity? there can only be one entity in this file | |
| Oct 8, 2017 at 18:14 | comment | added | sarthak | I would suggest don't modify this code, instead create another entity and instantiate two of these FLIPFLOP entities into that new entity and connect output of the second to the input of first as you want. | |
| Oct 8, 2017 at 17:40 | history | asked | super95 | CC BY-SA 3.0 |