Timeline for Synchronize Outputs of Separate FPGAs Within 1ns
Current License: CC BY-SA 3.0
4 events
| when toggle format | what | by | license | comment | |
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| Dec 7, 2017 at 17:54 | comment | added | Keegan Jay | OK, we understand each other. Thanks for the advice! | |
| Dec 7, 2017 at 17:53 | comment | added | Dan Mills | Device delay is not generally stable over temperature, and usually you have to do some automated lane alignment if running at anything like 1GHz DDR, this is easy when the protocol is designed to support it, but I get the impression we are talking timing application not data link here? Ovenised FPGAs....? The external flipflops provide a register that may have lower skew (and lower variability) then the FPGA itself, you would have to study the datasheets. | |
| Dec 7, 2017 at 17:47 | comment | added | Keegan Jay | Within the same BUFIO region, clock tree skew is actually 60ps, package skew is 95 ps. Propagation delay variability is an open question... If I can trim coax lengths (or use the tapped delays) are you saying that device variation is static and possible to calibrate out? This worries me less than variation over temperature of > 1ns. Finally, what is the advantage of the external flip flops? More precise timing specs? The Spartan 6 (-3 grade) can register data at 1 Gbps on all I/O pins. | |
| Dec 7, 2017 at 11:57 | history | answered | Dan Mills | CC BY-SA 3.0 |