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Dec 11, 2017 at 9:16 comment added user61665 In response to your 2nd suggestion: doesn't the ADPLL actually accumulates the phase differences from before to arrive at a new operating frequency for the DCO? Wouldn't changing the phase difference through modular arithmetic disrupt the operation of the ADPLL in some way? (Signal trajectory matters in my case, as I am using DPSK format modulation.) (1st suggestion increases the operating frequency of the CORDIC, not viable in my situation.)
Dec 11, 2017 at 6:58 history edited Neil_UK CC BY-SA 3.0
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Dec 11, 2017 at 6:53 history answered Neil_UK CC BY-SA 3.0