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Your fault is that your design specs are neglected. As a consequence, so is the margin to your operating conditions to specifications. Important things to consider are the margin to loss of CMRR where it stops working. The critical specs are input CM bias for a single supply;

• Vcc=5V

• Vio . . .1.7 typ 7 max. [+/- mV]
• CMRR 0 min -0.2 typ [V]

• All unused control inputs of the device must be held at VCC or GND to ensure proper device operation

The reason is that you are violating some parameter in the datasheet or the system design specs, such as;

• Min V drop and input offset error, noise error

• The input RMS noise levels can also degrade low current thresholds so this specification also comes into play

Recommendation

A design improvement adds some positive input Vcm margin to the inputs so that R2 is replaced with a circuit that moves from Gnd=0V to 1V

Pay attention to fine print on unused inputs and input offset voltage.

Your fault is that your design specs are neglected. As a consequence, so is the margin to your operating conditions to specifications. Important things to consider are the margin to loss of CMRR where it stops working. The critical specs are input CM bias for a single supply;

• Vcc=5V

• Vio . . .1.7 typ 7 max. [+/- mV]
• CMRR 0 min -0.2 typ [V]

• All unused control inputs of the device must be held at VCC or GND to ensure proper device operation

The reason is that you are violating some parameter in the datasheet or the system design specs, such as;

• Min V drop and input offset error, noise error

• The input RMS noise levels can also degrade low current thresholds so this specification also comes into play

Recommendation

A design improvement adds some positive input Vcm margin to the inputs so that R2 is replaced with a circuit that moves from Gnd=0V to 1V

Pay attention to fine print on unused inputs and input offset voltage.

There are many different classes of OA's but it may not be obvious.

• RRI ( input only)
• RRO ( output only) e.g. LMV358
• RRIO ( input and output)
• CM input extends to or past Negative Supply (LM358 = -0.3V) which is why this part did not fail

Your fault is that your design specs are too crude. ( don't care )

The reason is that you are violating some parameter in the datasheet or the system design specs, such as;

• Min V drop and input offset error, noise error

• Max Voltage drop and power dissipation in the current shunt

  • Since efficiency is affected by shunt loss and voltage drop with resulting power dissipation in the shunt, a shunt R is selected in IC shunt sensors for 50 to 100mV at max rated current.
  • the input offset voltage implies a limit for offset current error at the lowest desired current sense value, and typically 1% is easily achievable with less , it takes more effort, using BJT style OA's, laser trimmed for Vio, and chopper stabilized OA's that commutate the input and output to reduce the VIo levels even further

• The input RMS noise levels can also degrade low current thresholds so this specification also comes into play

• load resistance for R2 in CMOS which can induce an offset voltage if less than rated output of xx Kohm from the much higher output impedance of the CMOS Op Amp.

• lack of specs for threshold current.

  • generally for Pd reasons, shunts are selected for 75mV drop full scale and thus a 10% error can occur either the nominal input offset of CMOS and chooses Vio values of < x% of this such as 1% or maybe 10% in this "crude" case.

Your fault is that your design specs are neglected. As a consequence, so is the margin to your operating conditions to specifications. Important things to consider are the margin to loss of CMRR where it stops working. The critical specs are input CM bias for a single supply;

• Vcc=5V

• Vio . . .1.7 typ 7 max. [+/- mV]
• CMRR 0 min -0.2 typ [V]

• All unused control inputs of the device must be held at VCC or GND to ensure proper device operation

The reason is that you are violating some parameter in the datasheet or the system design specs, such as;

• Min V drop and input offset error, noise error

• The input RMS noise levels can also degrade low current thresholds so this specification also comes into play

Recommendation

A design improvement adds some positive input Vcm margin to the inputs so that R2 is replaced with a circuit that moves from Gnd=0V to 1V

Pay attention to fine print on unused inputs and input offset voltage.

CMOS Rail to Rail Op Amps must use a cross-conduction mode to bias the bipolar MOS driver in linear mode. This results in a much higher output impedance in linear mode than the current amplifiers of BJT complementary Darlingtons used in Op Amps. (OA) The result is the open loop output impedance of BJT OA's is at least 1 or 2 decades lower than CMOS rail to Rail OA's.

Your fault is that your design specs are too crude. ( don't care )

The reason is that you are violating some parameter in the datasheet or the system design specs, such as;

• Min V drop and input offset error, noise error

• Max Voltage drop and power dissipation in the current shunt

  • Since efficiency is affected by shunt loss and voltage drop with resulting power dissipation in the shunt, a shunt R is selected in IC shunt sensors for 50 to 100mV at max rated current.
  • the input offset voltage implies a limit for offset current error at the lowest desired current sense value, and typically 1% is easily achievable with less , it takes more effort, using BJT style OA's, laser trimmed for Vio, and chopper stabilized OA's that commutate the input and output to reduce the VIo levels even further

• The input RMS noise levels can also degrade low current thresholds so this specification also comes into play

• load resistance for R2 in CMOS which can induce an offset voltage if less than rated output of xx Kohm from the much higher output impedance of the CMOS Op Amp.

• lack of specs for threshold current.

  • generally for Pd reasons, shunts are selected for 75mV drop full scale and thus a 10% error can occur either the nominal input offset of CMOS and chooses Vio values of < x% of this such as 1% or maybe 10% in this "crude" case.

Your fault is that your design specs are too crude. ( don't care )

The reason is that you are violating some parameter in the datasheet or the system design specs, such as;

• Min V drop and input offset error, noise error

• Max Voltage drop and power dissipation in the current shunt

  • Since efficiency is affected by shunt loss and voltage drop with resulting power dissipation in the shunt, a shunt R is selected in IC shunt sensors for 50 to 100mV at max rated current.
  • the input offset voltage implies a limit for offset current error at the lowest desired current sense value, and typically 1% is easily achievable with less , it takes more effort, using BJT style OA's, laser trimmed for Vio, and chopper stabilized OA's that commutate the input and output to reduce the VIo levels even further

• The input RMS noise levels can also degrade low current thresholds so this specification also comes into play

• load resistance for R2 in CMOS which can induce an offset voltage if less than rated output of xx Kohm from the much higher output impedance of the CMOS Op Amp.

• lack of specs for threshold current.

  • generally for Pd reasons, shunts are selected for 75mV drop full scale and thus a 10% error can occur either the nominal input offset of CMOS and chooses Vio values of < x% of this such as 1% or maybe 10% in this "crude" case.