Timeline for Voltage across capacitor is shifted -20 VDC in PSPICE simulation
Current License: CC BY-SA 3.0
7 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Dec 21, 2017 at 14:14 | comment | added | dejoker | Yes, it is. I'm modeling a practical AC sinusoidal current source (1 ideal current source // big resistor) | |
| Dec 21, 2017 at 14:13 | comment | added | user16324 | Then are you sure that is a current source? | |
| Dec 21, 2017 at 13:59 | comment | added | dejoker | Thank Brian. The initial condition is Vc(t=0s)=0V. I did try to run over 10 * time constant but the result didn't change. | |
| Dec 21, 2017 at 13:31 | answer | added | pipe | timeline score: 3 | |
| Dec 21, 2017 at 13:30 | comment | added | user16324 | You either haven't simulated for long enough - or RC is too large. Try simulating for 10 * RC (you may want to reduce R to less than 1G :-) Once you understand that, there may be fixes involving different initial conditions... | |
| Dec 21, 2017 at 13:23 | review | First posts | |||
| Dec 21, 2017 at 13:42 | |||||
| Dec 21, 2017 at 13:22 | history | asked | dejoker | CC BY-SA 3.0 |