Timeline for Determining Operational Amplifier Offset Voltage
Current License: CC BY-SA 3.0
13 events
| when toggle format | what | by | license | comment | |
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| Feb 20, 2018 at 10:55 | comment | added | Tako | @Sven B It sounded like no Miller compensation at all, e.g. indirect compensation method or anything different than Miller compensation :D. Yes, that's fine. In practical designs zero nulling resistor Rz is added in series with Miller capacitance Cm. | |
| Feb 20, 2018 at 8:21 | comment | added | Sven B | @Tako, I meant versions with just a Miller capacitance. | |
| Feb 20, 2018 at 8:04 | comment | added | Sven B | A more practical implementation will add a resistance in series with the Miller capacitance. This introduces an extra zero that helps stability. | |
| Feb 18, 2018 at 23:25 | comment | added | Tako | @Sven B Miller compensation may and is used, MIM capacitors as well as PMOS transistors (body, drain and source connected together) are used. | |
| Feb 18, 2018 at 23:22 | comment | added | Tako | The architecture used is fine. It is the architecture that is discussed in every analog IC design book. This architecture is very often referred to as an operational amplifier. The 3rd buffer stage may be used to make it a "real" operational amplifier, but in analog IC world it is very often not necessary as very often only high impedance loads are used, e.g. the gates of MOS transistors. 2nd stage is a high gain stage. This design is often simulated in SPICE or EDA tools. | |
| Feb 18, 2018 at 22:26 | comment | added | Nedvved | FiddyOhm, your answer gave me some hints on how it should have been done, thanks. Sparky, indeed what I was doing in the design - my M7 size is about 3x M5 W/L, which gives 3x bigger current. Generally I don't think anything is missing in my design, everything was calculated primarily according to Allen Holberg's CMOS Design book, and additionally adjusted after simulations, which led to meeting most specifications. My problem was mainly with simulation techniques. Sven B, can you tell me what is beign used instead of miller capacitance in real life implementation? | |
| Feb 18, 2018 at 22:16 | vote | accept | Nedvved | ||
| Feb 18, 2018 at 22:02 | vote | accept | Nedvved | ||
| Feb 18, 2018 at 22:02 | |||||
| Feb 18, 2018 at 19:36 | comment | added | Sven B | And having the same bias voltage does not imply equal/less current. You can increase the W/L of M7 to scale the current. | |
| Feb 18, 2018 at 19:35 | comment | added | Sven B | @Sparky256 This is a very typical 2-stage Miller-compensated OTA (it is not an Opamp). The only difference with a real-life implementation will be that you never use that type of Miller compensation. Versions using a Miller-capacitor are typically used as an educational example. | |
| Feb 18, 2018 at 11:57 | comment | added | FiddyOhm | Sparky: You are very probably correct. I am not a discrete transistor designer, but I know op-amps very well. I am simply answering the OP's question, which seems to me to be in essence: How do you measure input offset voltage of an op-amp. | |
| Feb 18, 2018 at 5:14 | comment | added | user105652 | The OP does not have a good design to begin with. M5 and M7 cannot have the same bias voltage. M7 makes the output class A with little drive current. The middle-section high-gain stage is missing. A Spice model of this is likely to be a mess. | |
| Feb 18, 2018 at 2:39 | history | answered | FiddyOhm | CC BY-SA 3.0 |