Timeline for Jitter measurement in High speed serial link - Random jitter mean not 0
Current License: CC BY-SA 3.0
16 events
| when toggle format | what | by | license | comment | |
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| Mar 1, 2018 at 17:11 | comment | added | D.A.S. | The PJ is synchronous to something?? compute the delta peaks -0.7 -0.4 0 0.33 0.67 0.8 The skew is larger on +ve side | |
| Mar 1, 2018 at 17:05 | comment | added | Franz Forstmayr | i make a active compensation of ISI with pre-emphasis enabled, but the mean of -1ps is not affected in this case. | |
| Mar 1, 2018 at 17:02 | comment | added | D.A.S. | In old disk drive days with MFM worst case pattern was 110 or 6DB for ISI. But your peaks are spaced only 5%T which smacks of connector reflections to me. Still the asymmetry is unknown. @FranzForstmayr | |
| Mar 1, 2018 at 11:00 | comment | added | D.A.S. | Also consider auto-EQ tests on channel with RLL to narrow the 6 sigma jitter | |
| Mar 1, 2018 at 10:51 | comment | added | Franz Forstmayr | No flexible cables, not from pasternack. I'll do an sweep with the vna, thanks for your effort. | |
| Mar 1, 2018 at 10:29 | comment | added | D.A.S. | in that case, the mean is defined differently , bit over say the time constant of the PLL but rather computed over all the bits centering on peak jitter not mean. Are you using semi rigid cables? or ones from Pasternack ugh. Do a s11 s22 sweep | |
| Mar 1, 2018 at 10:23 | comment | added | Franz Forstmayr | So this means, that the error could be a result of the clock regeneration in the scope? (second order PLL) | |
| Mar 1, 2018 at 10:21 | history | edited | D.A.S. | CC BY-SA 3.0 |
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| Mar 1, 2018 at 10:15 | comment | added | D.A.S. | A non-zero mean implies your sync clock has a constant phase offset error. from some source | |
| Mar 1, 2018 at 10:13 | history | edited | D.A.S. | CC BY-SA 3.0 |
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| Mar 1, 2018 at 10:06 | comment | added | D.A.S. | The mesurement system must not be synchronous to data rate. Change cable length to see if return loss shifts some of the peaks. Precompensate your tx data. I just suggest things to check.. You can report back on which were relevant | |
| Mar 1, 2018 at 9:59 | vote | accept | Franz Forstmayr | ||
| Mar 1, 2018 at 9:52 | comment | added | D.A.S. | yes it can if ISI is non symmetrical . try different patterns (RLL?) and find worst case, best case | |
| Mar 1, 2018 at 9:51 | history | edited | D.A.S. | CC BY-SA 3.0 |
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| Mar 1, 2018 at 9:47 | comment | added | Franz Forstmayr | Sorry if i was unclear: I was asking about the non zero mean of my random jitterl, so this should not be affected from ISI or pattern. | |
| Mar 1, 2018 at 9:43 | history | answered | D.A.S. | CC BY-SA 3.0 |