Timeline for Real current return path
Current License: CC BY-SA 3.0
6 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Mar 15, 2018 at 14:26 | comment | added | damien | Yes, my trouble is if from the Vss pin it goes through the capacitor then to the PWR plane it means that the (impedance of the capacitor + impedance of the loop created on the PWR plane)<impedance of the loop created by going directly to the GND plane | |
| Mar 14, 2018 at 13:19 | comment | added | Andy aka | Do you mean "the impedance of the capacitor"? | |
| Mar 14, 2018 at 13:17 | comment | added | damien | Obviously they have both connections GND and Vcc but the current in U4 flows from Rx to GND pin not Vdd pin. And the second part is exactly my question does the current path by the decoupling capacitor? Because if it does, it means the inductance of the capacitor is smaller than the inductance of the loop created if you go to the GND plane | |
| Mar 14, 2018 at 11:09 | comment | added | Andy aka | All chips must have GND and Vcc connections to ground planes and power planes. Your diagram doesn't seem to show that. All chips in a situation like this should have supply decouplers. Your diagram doesn't appear to show this. GP and PP are capacitively coupled naturally plus, add on all the decouplers and PP and GP share AC signal currents (irrespective of DC voltage differences). | |
| Mar 14, 2018 at 10:56 | comment | added | damien | I added a drawing for clarification. But I understand the theory that the current go through the path with the smallest inductance the question is how does it jump from the Vss pin to the PWR plane because it has to pass by somewhere. How bigger is the loop to go the GND plane compared to this jump by I do not know where. | |
| Mar 8, 2018 at 12:16 | history | answered | Andy aka | CC BY-SA 3.0 |