Timeline for Help with BJT-based driver for MOSFET
Current License: CC BY-SA 3.0
20 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Mar 11, 2018 at 0:07 | answer | added | jonk | timeline score: 3 | |
| Mar 10, 2018 at 23:41 | answer | added | D.A.S. | timeline score: 0 | |
| Mar 10, 2018 at 23:37 | comment | added | jonk | @GrigBetsan I'll give it a shot. I have my type of hammer and saw. Others will have theirs. So you may get different approaches. Choose what makes you feel better if you see more than one approach. | |
| Mar 10, 2018 at 23:36 | comment | added | Grig Betsan | I think edge can be more than 100ns... 400ns I guess, maybe little bit more, but I still don't know how to achieve this | |
| Mar 10, 2018 at 23:35 | comment | added | jonk | @GrigBetsan I was thinking just a smidge higher (at about 350 mA) than Tony points out, but he's right. That's probably where the peak current will be. The good thing is that this only happens at the edges. So the average will be a lot less. But you still have to support the peaks, too. Hand construction is going to be a problem. Providing a local resource for charge will be needed I'm sure (bypass caps.) You are nearing 10 MHz territory so I'd dead-bug the construction. No way would I consider a protoboard. | |
| Mar 10, 2018 at 23:31 | comment | added | D.A.S. | taking 10~90% of 12V roughly C dV/dt~3nF 10V/0.1us=Ic=300mA so Rce <=10V/300mA=33 Ohms... So an LM555 may (almost) do it | |
| Mar 10, 2018 at 23:27 | comment | added | Grig Betsan | Pulse width shouldn't be very precise. Since I want to use TO-92 packaged BJTs, so current through them should not exceed 250mA, but as far as I understand, 250mA is not sufficient for such sharp edges, right? | |
| Mar 10, 2018 at 23:26 | comment | added | jonk | @GrigBetsan 100ns edges will be ... hard ... with discrete parts. The gate capacitance will be easy. | |
| Mar 10, 2018 at 23:18 | comment | added | Grig Betsan | Gate capacitance will be up to 3nF, I want ~100ns edges, or close to this. I am newbie at EE, especially on BJTs | |
| Mar 10, 2018 at 23:11 | comment | added | D.A.S. | A CMOS level shifter is required with known source RdsOn about 1% of Rdson of driver FETs This takes care of RC time constant and CissRdsOn relationship for power FET | |
| Mar 10, 2018 at 23:07 | comment | added | jonk | @TonyStewart.EEsince'75 Yeah. That too. There exists an unspecified load. That's for sure. Must be remedied. | |
| Mar 10, 2018 at 23:07 | comment | added | D.A.S. | Ciss must be defined | |
| Mar 10, 2018 at 23:06 | comment | added | jonk | How sharp do you want your edges? If you are modifying the pulse width at this rate, how precise do you need to be? These are serious questions that need to be answered. | |
| Mar 10, 2018 at 23:06 | comment | added | D.A.S. | V Gain required<4 , level shift required. Wrong topology | |
| Mar 10, 2018 at 23:02 | comment | added | jonk | @GrigBetsan Not by emitter-following. That's for certain. You will have one BE drop from your MCU voltage rail, at best, at the output. You must modify your topology. And given the 70+ kHz you want, you must start to look more at parasitics, too. 100 kHz isn't hard. But it is moving into the area where lots of other considerations factor in. The slew rates start looking pretty darned fast. | |
| Mar 10, 2018 at 23:01 | comment | added | Grig Betsan | @jonk, I am expecting amplified 0-12V signal on output, how I can achieve this? | |
| Mar 10, 2018 at 22:50 | comment | added | D.A.S. | define your goal with Vout output and current limit. You only get Vbe drops from 3.3 giving 0.7 to 2.6 out | |
| Mar 10, 2018 at 22:43 | comment | added | jonk | Q1 is merely emitter-following your input PWM. What else should you expect? | |
| Mar 10, 2018 at 22:39 | review | First posts | |||
| Mar 10, 2018 at 22:55 | |||||
| Mar 10, 2018 at 22:34 | history | asked | Grig Betsan | CC BY-SA 3.0 |