Timeline for Convert parallel LVDS to csi-2
Current License: CC BY-SA 3.0
6 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 9, 2018 at 12:17 | comment | added | alex.forencich | @oldfart the toolchains aren't free for all FPGAs; usually only the smaller ones. Also, the FPGA vendor supplied CSI IP cores probably aren't free. | |
| Apr 7, 2018 at 16:47 | comment | added | asdfex | @oldfart: They are not free. Lattice requires a payed license for the larger FPGAs (those with SERDES mostly) | |
| Apr 7, 2018 at 11:36 | comment | added | asdfex | It all depends on the speed - what is the data rate per lane? | |
| Apr 7, 2018 at 10:41 | comment | added | Oldfart | AFAIK All FPGA tools are free these days. Lattice definitely, I have it. There is no simple solution CSI is a complex analogue protocol, a mixture of LVDS and I2C. I think Xilinx have managed to use two pairs of I/O pins in different modes which work. | |
| Apr 7, 2018 at 10:26 | comment | added | Andy aka | Have you tried googling for answers? | |
| Apr 7, 2018 at 10:16 | history | asked | user1175197 | CC BY-SA 3.0 |