Skip to main content

Timeline for Hamming Code Circuit

Current License: CC BY-SA 4.0

11 events
when toggle format what by license comment
Nov 14, 2020 at 5:06 history bumped CommunityBot This question has answers that may be good or bad; the system has marked it active so that they can be reviewed.
Jul 15, 2020 at 22:00 history bumped CommunityBot This question has answers that may be good or bad; the system has marked it active so that they can be reviewed.
Mar 15, 2020 at 9:02 history bumped CommunityBot This question has answers that may be good or bad; the system has marked it active so that they can be reviewed.
Oct 24, 2019 at 10:01 history bumped CommunityBot This question has answers that may be good or bad; the system has marked it active so that they can be reviewed.
Jun 21, 2019 at 3:01 history bumped CommunityBot This question has answers that may be good or bad; the system has marked it active so that they can be reviewed.
Feb 16, 2019 at 0:03 history bumped CommunityBot This question has answers that may be good or bad; the system has marked it active so that they can be reviewed.
Jun 9, 2018 at 16:06 answer added jonk timeline score: 2
Jun 9, 2018 at 8:25 comment added Leonel Yes, the remaining possibilities are 011 (I1), 110 (I2), 111 (I3) and 101 (I4). Now with this information I can make a truth table with 3 imputs (S1, S2, S3) and 4 outputs, each output will be applied in a XOR gate along with each data bit. When the inputs are 000, 001, 010, 100 I will want no changes in my data bits, the rest of the inputs will have an specific output that will fix any erroneous data bit. For example, if the inputs are 110 (I2), then the desired outputs will be i1=0, i2=1, i3=0, i4=0 (0100), this secures that the bit I2 will be the one corrected. I understand it now, thanks.
Jun 9, 2018 at 6:36 comment added jonk You've already got the generators: \$P_N\$. Apply them to their three inputs from the received data and compare their outputs with the received parity bits. (XOR?) These comparisons have eight possibilities. If all three are 0, no error. Otherwise, you have 7 possible error conditions. But if only one of the comparison outputs is 1 (the other are 0) then it's the parity bit that went wrong. So no data change. This leaves only ... hmm... shocking? ... Four remaining possibilities!! Can you work out what that means?
Jun 9, 2018 at 6:14 review First posts
Jun 9, 2018 at 10:03
Jun 9, 2018 at 6:11 history asked Leonel CC BY-SA 4.0