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Jun 21, 2018 at 15:10 comment added D.A.S. The Ciss of both FETs and R3+R2 form a slow turn off time to prevent false triggering from some FETs with high Miller capacitance self trigger due to dV/dt rise.
Jun 21, 2018 at 15:06 comment added Drew I would consider R3 to be the "pull-up" and R2 to be a current limiting resistor. Why R2 is so large, I don't know. I would have put a 10k in there max.
Jun 21, 2018 at 12:27 comment added D.A.S. Ie your analogy of the nail or analysis hitting the target therefore is bent . R3 carries “no power “ , certainly no more than R2 +R3 and Q3 or about a microwatt , so I would edit out that he nailed it. Because he did not. It’s important to correct your own mistakes as I just did
Jun 21, 2018 at 11:39 comment added D.A.S. Actually we all ignored that R2 is essential for pullup too and without it R3 cannot touch the gates
Jun 21, 2018 at 4:44 history answered Drew CC BY-SA 4.0