Timeline for Verilog - connecting multiple bidirectional buses
Current License: CC BY-SA 4.0
6 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jul 4, 2018 at 19:55 | vote | accept | Triforcer | ||
| Jul 4, 2018 at 19:28 | comment | added | Ale..chenski | Apparently the Verilog compiler can't make sense of what do you mean, and is looking for a driver. My Verilog is rusty, and I need to look into my projects of 10-years old to find the right language structures for you, and I feel lazy. See the Oldfart answer. | |
| Jul 4, 2018 at 19:25 | comment | added | Triforcer | That's true, I thought it looked odd, but what I wanted to say was that CPUdataBus should just be "itself" when it's acting as an output. If that makes sense | |
| Jul 4, 2018 at 19:21 | comment | added | Ale..chenski | You have a conflicting statement: when "write" is true, the CPUdataBus is driven by itself. | |
| Jul 4, 2018 at 19:20 | answer | added | Oldfart | timeline score: 4 | |
| Jul 4, 2018 at 19:10 | history | asked | Triforcer | CC BY-SA 4.0 |