Timeline for VHDL: ADC to USB Buffering using Fifo
Current License: CC BY-SA 4.0
5 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Oct 1, 2018 at 19:37 | vote | accept | nandflash1 | ||
| Oct 1, 2018 at 19:36 | comment | added | nandflash1 | I get it now. For the code i posted, even if the write enable and read enable both become logic high the process will first do one if loop and then do the second if loop and both read and write will be served in one clock cycle. Since the process's inside is sequential i tought it cannot serve. Now there is no problem then. I can use fifo deisgn to buffer adc to usb without any problem. Thank you again | |
| Oct 1, 2018 at 19:25 | comment | added | Dave Tweed | Both the Xilinx IP FIFO and the FIFO you linked to are perfectly capable of doing reads and writes simultaneously. Have you seen any indication that they can't? | |
| Oct 1, 2018 at 19:07 | comment | added | nandflash1 | Thank you. Are you talking about the fifo design that is coming with xilinx ip ore's fifo generator (for serving different processes at the same time). For example the fifo code that i refered with link is not a design that can serve both read and write simultaneously right. | |
| Sep 30, 2018 at 21:18 | history | answered | Dave Tweed | CC BY-SA 4.0 |