Timeline for Sub microsecond jitter accuracy - what to use?
Current License: CC BY-SA 4.0
21 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Mar 8 at 14:15 | vote | accept | ignoramusextraordinaire | ||
| Oct 2, 2018 at 13:08 | comment | added | Jon Custer | I'm presuming that a digital delay generator is overkill for your project? What are your requirements? | |
| Oct 2, 2018 at 1:53 | answer | added | akohlsmith | timeline score: 3 | |
| Oct 1, 2018 at 23:18 | comment | added | Cort Ammon | "... a typical way to get the accuracy and resolution I’m looking for. " It would help if you provided us the accuracy and resolution you are looking for. Are you just looking for "submicrosecond" i.e. less than 1us, or do you actually have a more strict requirement? | |
| Oct 1, 2018 at 21:23 | answer | added | Graham | timeline score: 1 | |
| Oct 1, 2018 at 15:01 | history | tweeted | twitter.com/StackElectronix/status/1046777145270374401 | ||
| Oct 1, 2018 at 14:22 | comment | added | D.A.S. | Even a lowly 32kHz Xtal to sync outputs has a period of 31 us and jitter of xxx ns using yyy logic. Is deadtime involved? in x us range? | |
| Oct 1, 2018 at 14:13 | answer | added | Dmitry Grigoryev | timeline score: 4 | |
| Oct 1, 2018 at 14:12 | comment | added | Dave Tweed | "In the past with an 8 bit micro... " 8-bit micros still exist. Some of them are very fast. Why wouldn't you use one? | |
| Oct 1, 2018 at 13:52 | comment | added | D.A.S. | You start with a state machine with timing requirements on all inputs and outputs then sync to a stable clock to eliminate jitter, then choose a solution. Not the other way around. i.e. bottoms up then for other reasons, top-down to arrive a cost-effective solution | |
| Oct 1, 2018 at 13:39 | answer | added | gregb212 | timeline score: 2 | |
| Oct 1, 2018 at 13:27 | comment | added | Lundin | It would help if you can specify exactly which part you are using. By pipelining, do you actually mean branch prediction? As in, a part with cache memory might get indeterministic behavior when branch prediction fails. Particularly when flash & wait states is involved. Because pipelining shouldn't cause jitter, but rather just make the code faster overall. And pipelining has been around since long before ARM, so your old MCU probably had some flavour of it. | |
| Oct 1, 2018 at 13:23 | answer | added | Lundin | timeline score: 6 | |
| Oct 1, 2018 at 13:08 | answer | added | Olin Lathrop | timeline score: 15 | |
| Oct 1, 2018 at 13:03 | comment | added | Olin Lathrop | It would help to have a spec or at least some examples of what signal have to be generate as a result of what other signals, with minimum and maximum allowable edge timing. | |
| Oct 1, 2018 at 13:03 | answer | added | Dan Mills | timeline score: 5 | |
| Oct 1, 2018 at 13:02 | comment | added | Scott Seidman | Pipelining will cause 10 clock ticks of jitter??? | |
| Oct 1, 2018 at 12:57 | history | edited | winny | CC BY-SA 4.0 |
Microseconds, not microsiemens
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| Oct 1, 2018 at 12:47 | comment | added | Lelesquiz | FPGAs will do the trick | |
| Oct 1, 2018 at 12:40 | review | First posts | |||
| Oct 1, 2018 at 13:00 | |||||
| Oct 1, 2018 at 12:40 | history | asked | ignoramusextraordinaire | CC BY-SA 4.0 |