To achieve even lower inductance, widen either or both of VDD and GND traces (neither traces are a large region of copper metal, or foil as used in fabricating the PCB, so neither is a "plane"). By using that 1mm minimum separation all along that region, you will better exploit those two capacitors in supplying transient currents to the microcontroller.

To achieve even lower inductance, widen either or both of VDD and GND traces (neither traces are a large region of copper metal, or foil as used in fabricating the PCB, so neither is a "plane"). By using that 1mm minimum separation all along that region, you will better exploit those two capacitors in supplying transient currents to the microcontroller.

^{simulate this circuit – Schematic created using CircuitLab}