Revisions to problem with 6 bit adder

Post Reopened by Michel Keijzers, Dave Tweed

occurred Feb 15, 2019 at 19:23

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edited Feb 15, 2019 at 17:43

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`timescale 1ns/ 1ps
module sixbit_ripple_adder
(
input wire[5:0] x,y,
input wire sel,
output wire overflow, c_out,
output wire[5:0] sum
) ;

wire c1,c2,c3,c4,c5,c6 ;

FullAdder f1 ( .a(x[0]) , .b(y[0]^sel) , .cin(sel) , .s(sum[0]) , .cout(c1) ) ;
FullAdder f2 ( .a(x[1]) , .b(y[1]^sel) , .cin(c1) , .s(sum[1]) , .cout(c1c2) ) ;
FullAdder f3 ( .a(x[2]) , .b(y[2]^sel) , .cin(c2) , .s(sum[2]) , .cout(c1c3) ) ;
FullAdder f4 ( .a(x[3]) , .b(y[3]^sel) , .cin(c3) , .s(sum[3]) , .cout(c1c4) ) ;
FullAdder f5 ( .a(x[4]) , .b(y[4]^sel) , .cin(c4) , .s(sum[4]) , .cout(c1c5) ) ;
FullAdder f6 ( .a(x[5]) , .b(y[5]^sel) , .cin(c5) , .s(sum[5]) , .cout(c1c6) ) ;
assign c_out = c6 ;
assign overflow = c5^c6 ;

endmodule

`timescale 1ns/ 1ps
module sixbit_ripple_adder
(
input wire[5:0] x,y,
input wire sel,
output wire overflow, c_out,
output wire[5:0] sum
) ;

wire c1,c2,c3,c4,c5,c6 ;

FullAdder f1 ( .a(x[0]) , .b(y[0]^sel) , .cin(sel) , .s(sum[0]) , .cout(c1) ) ;
FullAdder f2 ( .a(x[1]) , .b(y[1]^sel) , .cin(c1) , .s(sum[1]) , .cout(c1) ) ;
FullAdder f3 ( .a(x[2]) , .b(y[2]^sel) , .cin(c2) , .s(sum[2]) , .cout(c1) ) ;
FullAdder f4 ( .a(x[3]) , .b(y[3]^sel) , .cin(c3) , .s(sum[3]) , .cout(c1) ) ;
FullAdder f5 ( .a(x[4]) , .b(y[4]^sel) , .cin(c4) , .s(sum[4]) , .cout(c1) ) ;
FullAdder f6 ( .a(x[5]) , .b(y[5]^sel) , .cin(c5) , .s(sum[5]) , .cout(c1) ) ;

`timescale 1ns/ 1ps
module sixbit_ripple_adder
(
input wire[5:0] x,y,
input wire sel,
output wire overflow, c_out,
output wire[5:0] sum
) ;

wire c1,c2,c3,c4,c5,c6 ;

FullAdder f1 ( .a(x[0]) , .b(y[0]^sel) , .cin(sel) , .s(sum[0]) , .cout(c1) ) ;
FullAdder f2 ( .a(x[1]) , .b(y[1]^sel) , .cin(c1) , .s(sum[1]) , .cout(c2) ) ;
FullAdder f3 ( .a(x[2]) , .b(y[2]^sel) , .cin(c2) , .s(sum[2]) , .cout(c3) ) ;
FullAdder f4 ( .a(x[3]) , .b(y[3]^sel) , .cin(c3) , .s(sum[3]) , .cout(c4) ) ;
FullAdder f5 ( .a(x[4]) , .b(y[4]^sel) , .cin(c4) , .s(sum[4]) , .cout(c5) ) ;
FullAdder f6 ( .a(x[5]) , .b(y[5]^sel) , .cin(c5) , .s(sum[5]) , .cout(c6) ) ;
assign c_out = c6 ;
assign overflow = c5^c6 ;

endmodule

fix formatting

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edited Feb 15, 2019 at 17:08

Dave Tweed

178.3k
17
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Calculation that I did on pen and paper: x = 111111, y = 100000 y'+1 = 100000

x + y' + 1 = 011111 with Carry out = 1 and overflow = ex-or of 1 and 0 = 1

x = 000000, y = 000000 y'+1 = 000000

x + y' + 1 = 000000 with carry out = 0 and overflow = ex-or of 0 and 0 = 0

x = 111111, y = 100000
y'+1 = 100000

x + y' + 1 = 011111 with Carry out = 1 and overflow = ex-or of 1 and 0 = 1

x = 000000, y = 000000
y'+1 = 000000

x + y' + 1 = 000000 with carry out = 0 and overflow = ex-or of 0 and 0 = 0

My code is this: Full 1bit Adder:

My code is this: 
Full 1bit Adder:

module FullAdder( a,b,cin,s,cout ) ;
input wire a,b,cin ;
output wire s,cout ;
assign s = cin^a^b; 
assign cout = (b&cin) | (a&cin) | (a&b) ;
 
endmodule 

Code for 6 bit adder:

Code for 6 bit adder:

`timescale 1ns/ 1ps
module sixbit_ripple_adder
(
input wire[5:0] x,y,
input wire sel,
output wire overflow, c_out,
output wire[5:0] sum
) ;

wire c1,c2,c3,c4,c5,c6 ;

FullAdder f1 ( .a(x[0]) , .b(y[0]^sel) , .cin(sel) , .s(sum[0]) , 
 .cout(c1) ) ;
FullAdder f2 ( .a(x[1]) , .b(y[1]^sel) , .cin(c1) , .s(sum[1]) , 
 .cout(c1) ) ;
FullAdder f3 ( .a(x[2]) , .b(y[2]^sel) , .cin(c2) , .s(sum[2]) , 
 .cout(c1) ) ;
FullAdder f4 ( .a(x[3]) , .b(y[3]^sel) , .cin(c3) , .s(sum[3]) , 
 .cout(c1) ) ;
FullAdder f5 ( .a(x[4]) , .b(y[4]^sel) , .cin(c4) , .s(sum[4]) , 
 .cout(c1) ) ;
FullAdder f6 ( .a(x[5]) , .b(y[5]^sel) , .cin(c5) , .s(sum[5]) ,   
 .cout(c1) ) ;

What am I missing ?

Any help is highly appreciated.

Thanks.

Calculation that I did on pen and paper: x = 111111, y = 100000 y'+1 = 100000

x + y' + 1 = 011111 with Carry out = 1 and overflow = ex-or of 1 and 0 = 1

x = 000000, y = 000000 y'+1 = 000000

x + y' + 1 = 000000 with carry out = 0 and overflow = ex-or of 0 and 0 = 0

My code is this: 
Full 1bit Adder:

module FullAdder( a,b,cin,s,cout ) ;
input wire a,b,cin ;
output wire s,cout ;
assign s = cin^a^b; 
assign cout = (b&cin) | (a&cin) | (a&b) ;
 
endmodule 

Code for 6 bit adder:

`timescale 1ns/ 1ps
module sixbit_ripple_adder
(
input wire[5:0] x,y,
input wire sel,
output wire overflow, c_out,
output wire[5:0] sum
) ;

wire c1,c2,c3,c4,c5,c6 ;

FullAdder f1 ( .a(x[0]) , .b(y[0]^sel) , .cin(sel) , .s(sum[0]) , 
 .cout(c1) ) ;
FullAdder f2 ( .a(x[1]) , .b(y[1]^sel) , .cin(c1) , .s(sum[1]) , 
 .cout(c1) ) ;
FullAdder f3 ( .a(x[2]) , .b(y[2]^sel) , .cin(c2) , .s(sum[2]) , 
 .cout(c1) ) ;
FullAdder f4 ( .a(x[3]) , .b(y[3]^sel) , .cin(c3) , .s(sum[3]) , 
 .cout(c1) ) ;
FullAdder f5 ( .a(x[4]) , .b(y[4]^sel) , .cin(c4) , .s(sum[4]) , 
 .cout(c1) ) ;
FullAdder f6 ( .a(x[5]) , .b(y[5]^sel) , .cin(c5) , .s(sum[5]) ,   
 .cout(c1) ) ;

What am I missing ?

Any help is highly appreciated.

Thanks.

Calculation that I did on pen and paper:

x = 111111, y = 100000
y'+1 = 100000

x + y' + 1 = 011111 with Carry out = 1 and overflow = ex-or of 1 and 0 = 1

x = 000000, y = 000000
y'+1 = 000000

x + y' + 1 = 000000 with carry out = 0 and overflow = ex-or of 0 and 0 = 0

My code is this: Full 1bit Adder:

module FullAdder( a,b,cin,s,cout ) ;
input wire a,b,cin ;
output wire s,cout ;
assign s = cin^a^b; 
assign cout = (b&cin) | (a&cin) | (a&b) ;
endmodule

Code for 6 bit adder:

`timescale 1ns/ 1ps
module sixbit_ripple_adder
(
input wire[5:0] x,y,
input wire sel,
output wire overflow, c_out,
output wire[5:0] sum
) ;

wire c1,c2,c3,c4,c5,c6 ;

FullAdder f1 ( .a(x[0]) , .b(y[0]^sel) , .cin(sel) , .s(sum[0]) , .cout(c1) ) ;
FullAdder f2 ( .a(x[1]) , .b(y[1]^sel) , .cin(c1) , .s(sum[1]) , .cout(c1) ) ;
FullAdder f3 ( .a(x[2]) , .b(y[2]^sel) , .cin(c2) , .s(sum[2]) , .cout(c1) ) ;
FullAdder f4 ( .a(x[3]) , .b(y[3]^sel) , .cin(c3) , .s(sum[3]) , .cout(c1) ) ;
FullAdder f5 ( .a(x[4]) , .b(y[4]^sel) , .cin(c4) , .s(sum[4]) , .cout(c1) ) ;
FullAdder f6 ( .a(x[5]) , .b(y[5]^sel) , .cin(c5) , .s(sum[5]) , .cout(c1) ) ;

What am I missing?

added 835 characters in body

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edited Feb 15, 2019 at 16:24

shikhar

11
5

I have created the circuit in Vivado. The link for the codeCalculation that I useddid on pen and my test cases can be found herepaper: x = 111111, y = 100000 y'+1 = 100000

x + y' + 1 = 011111 with Carry out = 1 and overflow = ex-or of 1 and 0 = 1

x = 000000, y = 000000 y'+1 = 000000

x + y' + 1 = 000000 with carry out = 0 and overflow = ex-or of 0 and 0 = 0

What mistake I might be doing https://1drv.ms/f/s!AmyCvVHlJ4uYhTaBH9AaCgKkaaOL?

These two test cases are at time 1000I think it has to do something with 2s complements because 2s complement of 0000000 and 2800 ns respectively100000 are the numbers themselves.

Calculation that I did on pen and paper:have created the circuit in vivado.

xMy =code 111111is this: 
Full 1bit Adder:

module FullAdder( a,b,cin,s,cout y) ;
input wire a,b,cin ;
output wire s,cout ;
assign s = 100000cin^a^b; 
y'+1assign cout = 100000(b&cin) | (a&cin) | (a&b) ;

xendmodule +

Code y'for +6 1bit =adder:

`timescale 0111111ns/ with1ps
module Carrysixbit_ripple_adder
(
input outwire[5:0] =x,y,
input 1wire andsel,
output wire overflow, =c_out,
output ex-orwire[5:0] ofsum
) 1;

wire andc1,c2,c3,c4,c5,c6 0;

FullAdder =f1 1( .a(x[0]) , .b(y[0]^sel) , .cin(sel) , .s(sum[0]) , 
.cout(c1) ) ;
xFullAdder =f2 000000( .a(x[1]) , y.b(y[1]^sel) =, 000000.cin(c1) , .s(sum[1]) , 
y'+1.cout(c1) =) 000000;
FullAdder f3 ( .a(x[2]) , .b(y[2]^sel) , .cin(c2) , .s(sum[2]) , 
x.cout(c1) +) y';
FullAdder +f4 1( =.a(x[3]) 000000, with.b(y[3]^sel) carry, out.cin(c3) =, 0.s(sum[3]) and, overflow
.cout(c1) =) ex-or;
FullAdder off5 0( and.a(x[4]) 0, =.b(y[4]^sel) 0, .cin(c4) , .s(sum[4]) , 
.cout(c1) ) ;
FullAdder f6 ( .a(x[5]) , .b(y[5]^sel) , .cin(c5) , .s(sum[5]) ,   
.cout(c1) ) ;

What mistake I might be doing?

I think it has to do something with 2s complements because 2s complementValue of 0000000 and 100000 aresel for both the numbers themselvestest cases is 1.

What am I missing ?

Any help is highly appreciated.

Thanks.

I have created the circuit in Vivado. The link for the code I used and my test cases can be found here: https://1drv.ms/f/s!AmyCvVHlJ4uYhTaBH9AaCgKkaaOL

These two test cases are at time 1000 and 2800 ns respectively.

Calculation that I did on pen and paper:

x = 111111, y = 100000
y'+1 = 100000

x + y' + 1 = 011111 with Carry out = 1 and overflow = ex-or of 1 and 0 = 1

x = 000000, y = 000000
y'+1 = 000000

x + y' + 1 = 000000 with carry out = 0 and overflow = ex-or of 0 and 0 = 0

What mistake I might be doing?

I think it has to do something with 2s complements because 2s complement of 0000000 and 100000 are the numbers themselves.

What am I missing?

Calculation that I did on pen and paper: x = 111111, y = 100000 y'+1 = 100000

x + y' + 1 = 011111 with Carry out = 1 and overflow = ex-or of 1 and 0 = 1

x = 000000, y = 000000 y'+1 = 000000

x + y' + 1 = 000000 with carry out = 0 and overflow = ex-or of 0 and 0 = 0

What mistake I might be doing ?

I think it has to do something with 2s complements because 2s complement of 0000000 and 100000 are the numbers themselves.

I have created the circuit in vivado.

My code is this: 
Full 1bit Adder:

module FullAdder( a,b,cin,s,cout ) ;
input wire a,b,cin ;
output wire s,cout ;
assign s = cin^a^b; 
assign cout = (b&cin) | (a&cin) | (a&b) ;

endmodule 

Code for 6 bit adder:

`timescale 1ns/ 1ps
module sixbit_ripple_adder
(
input wire[5:0] x,y,
input wire sel,
output wire overflow, c_out,
output wire[5:0] sum
) ;

wire c1,c2,c3,c4,c5,c6 ;

FullAdder f1 ( .a(x[0]) , .b(y[0]^sel) , .cin(sel) , .s(sum[0]) , 
.cout(c1) ) ;
FullAdder f2 ( .a(x[1]) , .b(y[1]^sel) , .cin(c1) , .s(sum[1]) , 
.cout(c1) ) ;
FullAdder f3 ( .a(x[2]) , .b(y[2]^sel) , .cin(c2) , .s(sum[2]) , 
.cout(c1) ) ;
FullAdder f4 ( .a(x[3]) , .b(y[3]^sel) , .cin(c3) , .s(sum[3]) , 
.cout(c1) ) ;
FullAdder f5 ( .a(x[4]) , .b(y[4]^sel) , .cin(c4) , .s(sum[4]) , 
.cout(c1) ) ;
FullAdder f6 ( .a(x[5]) , .b(y[5]^sel) , .cin(c5) , .s(sum[5]) ,   
.cout(c1) ) ;

Value of sel for both the test cases is 1.

What am I missing ?

Any help is highly appreciated.

Thanks.

fix formatting

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edited Feb 15, 2019 at 16:17

Dave Tweed

178.3k
17
242
418

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added 444 characters in body

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edited Feb 15, 2019 at 16:09

shikhar

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Post Closed as "Needs details or clarity" by Dave Tweed

occurred Feb 15, 2019 at 16:01

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asked Feb 15, 2019 at 15:54

shikhar

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