Timeline for Passing usb data traces underneath of DCDC converter
Current License: CC BY-SA 4.0
6 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Feb 22, 2019 at 20:25 | comment | added | Adam Lawrence | Even worse - UART Rx and Tx are non-differential signals. | |
| Feb 22, 2019 at 20:21 | vote | accept | Berker Işık | ||
| Feb 22, 2019 at 18:53 | comment | added | Berker Işık | There is a mistake in the figure: lines should be UART TX/RX, instead of D+/D-. I mean, between Fpga and UART IC. | |
| Feb 22, 2019 at 17:30 | answer | added | D.A.S. | timeline score: 1 | |
| Feb 22, 2019 at 17:21 | comment | added | Peter Smith | The short answer; it is highly likely to interfere with USB, which is pretty brittle (for D+ and D- lines in particular) in the first place. | |
| Feb 22, 2019 at 17:04 | history | asked | Berker Işık | CC BY-SA 4.0 |