Timeline for Passing usb data traces underneath of DCDC converter
Current License: CC BY-SA 4.0
9 events
| when toggle format | what | by | license | comment | |
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| Feb 22, 2019 at 20:21 | vote | accept | Berker Işık | ||
| Feb 22, 2019 at 20:13 | history | edited | D.A.S. | CC BY-SA 4.0 |
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| Feb 22, 2019 at 20:08 | comment | added | D.A.S. | and signal slew rate? V/ns ? noise is 150mVp-p @ 20MHz BW Is it a USB 2.0 Full Speed device (12Mb/s) as opposed to a USB 2.0 High Speed device (480Mb/s).? THis matters and needs to be added to question | |
| Feb 22, 2019 at 20:02 | comment | added | D.A.S. | you mean can I look for you? What is your jitter tolerance? | |
| Feb 22, 2019 at 19:58 | comment | added | Berker Işık | Could you show an example source document in the style you mentioned, guarded uart traces. | |
| Feb 22, 2019 at 19:58 | history | edited | D.A.S. | CC BY-SA 4.0 |
added 432 characters in body
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| Feb 22, 2019 at 19:47 | comment | added | D.A.S. | If red is UART then UART is a CMOS 25~50 ohm unbalanced logic signal. so guarding may be necessary | |
| Feb 22, 2019 at 19:44 | comment | added | Berker Işık | I think, impedance matching needs between Connector and IC not for red lines in the figure. Red lines are Uart signals. | |
| Feb 22, 2019 at 17:30 | history | answered | D.A.S. | CC BY-SA 4.0 |