Timeline for Interval measurement in Verilog
Current License: CC BY-SA 4.0
4 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Feb 26, 2019 at 10:46 | comment | added | David Given | I don't get notified when the register gets read, and there is no DMA acknowledge. | |
| Feb 26, 2019 at 0:17 | comment | added | Dave Tweed | You could use the read of the register itself as the interrupt acknowledge (or DMA acknowledge, which is essentially the same thing). Or you could just assume that every interrupt gets handled within 9 clock periods and dispense with an explicit acknowledge. You'd just need another 4-bit counter to implement that. | |
| Feb 25, 2019 at 21:16 | comment | added | David Given | Yes, that's basically what I'm heading towards... unfortunately, there's a problem; I don't have a way to acknowledge interrupts! The module output interrupt line is in fact connected to a DMA controller drq line; this causes a read from a register attached to the data output. It doesn't generate acknowledgments, and neither does the status register. So, I don't think this problem is actually soluble inside the Verilog domain at all and I'll have to go with a proprietary Cypress UDB solution. | |
| Feb 24, 2019 at 16:57 | history | answered | Dave Tweed | CC BY-SA 4.0 |