Timeline for Can Cortex-A series ARM processors remap the physical address of DRAM via the Memory Controller?
Current License: CC BY-SA 4.0
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Mar 6, 2019 at 2:01 | answer | added | old_timer | timeline score: 1 | |
Mar 5, 2019 at 21:54 | comment | added | sherrellbc | @EugeneSh. Perhaps virtualization seen here with Xen is what I was looking for. This is EL2. The ability to remap the "world" as seen by a virtual machine under the control of a hypervisor. | |
Mar 5, 2019 at 20:50 | comment | added | sherrellbc | @ChrisStratton, Yes. I think I might just try to use QEMU rather than real hardware. There is real hardware that can do this, but I think it is more on the side of enterprise server-tier hardware, not SBCs (which is more in my price range or what I care to invest into a research project). | |
Mar 5, 2019 at 19:59 | comment | added | Chris Stratton | If you need to fake physical memory then you also need to fake whatever MMU (or naked startup mode and subsequent configuration) the code thinks it is manipulating to get at it. | |
Mar 5, 2019 at 19:18 | comment | added | sherrellbc | @EugeneSh. Thanks for the link. I am not so much a designer but rather hope to find a reasonably priced board that has such capabilities. Perhaps that link can provide enough information to help me search. Though I am not very optimistic. I think this might be a feature of more high-end appliances, like servers. | |
Mar 5, 2019 at 19:16 | comment | added | Eugene Sh. | A "Window" perhaps... Sorry, I am working with such a feature day-to-day, but I afraid the terminology might be our internal jargon and might contain confidential information. I found some similar controller from xilinx though: xilinx.com/support/documentation/ip_documentation/axi_epc/… | |
Mar 5, 2019 at 19:12 | comment | added | sherrellbc | @EugeneSh. Given that such a thing is a SoC feature, are there any keywords you are aware of that might help searching? Aperature is a good one to start with. It would help the process of combing through datasheets. | |
Mar 5, 2019 at 18:57 | comment | added | sherrellbc | @EugeneSh. I see. Aperature is perhaps a better word to describe the question. Thanks. | |
Mar 5, 2019 at 18:56 | history | edited | sherrellbc | CC BY-SA 4.0 |
added 202 characters in body; edited title
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Mar 5, 2019 at 18:55 | comment | added | Eugene Sh. | I guess you are not talking about MMU but about some controller able to provide an aperture from the ARM AXI address bus to some external address bus. If that's the case, then no, it a feature of a given SoC, not ARM. | |
Mar 5, 2019 at 18:54 | comment | added | sherrellbc | @ChrisStratton I was wondering if the use of an MMU implied the ability to relocate physical memory. I know this can be done with VM. And yes, of course. The intent is to develop an understanding of what does and does not work (via traps into the hypervisor) as the firmware runs. I do not expect it to just work out of the box. | |
Mar 5, 2019 at 18:53 | comment | added | sherrellbc | @EugeneSh. Of course, but can it be reprogrammed is what I am wondering. That is to say, can the base address of physical memory be mapped to something other than the default on power up. You can do this on x86. | |
Mar 5, 2019 at 18:31 | comment | added | Marcus Müller | yup, for example the second paragraph of the wikipedia article on the Cortex-A core says that and cites sources. | |
Mar 5, 2019 at 18:30 | comment | added | Chris Stratton | I'd expect that in specific would be possible if the firmware were willing to run entirely in the context of virtual addresses, but you may face larger problems getting a "firmware" to run on the wrong hardware. It might make more sense to run it in a virtual machine (yes, you can run qemu on arm hardware) or to analyze and modify the binary to alter the occasional absolute addresses, along with figuring out whatever other issues there may be. | |
Mar 5, 2019 at 18:29 | comment | added | Eugene Sh. | MMU (if you are referring to it) is an integral part of any Cortex-A core. | |
Mar 5, 2019 at 18:26 | history | asked | sherrellbc | CC BY-SA 4.0 |