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D.A.S.
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Consider what happens when you increase \$Vin \cdot10\$. The voltage slew rate also increases \$dV/dt=I/C\$ just when the Zener conducts. But increasing current x10 also increases R4 power \$(I^2R)\cdot100\$, so the designer forgot to include this in calculations.

This topology has poor characteristics for line voltage and should be avoided.

Replacing R4 with an ICL can prevent inrush currents but is still very inefficient.

An SCR regulator or better a buck forward or flyback regulator is best.

Even better is ZVS offline regulator with active PFC!

Consider what happens when you increase \$Vin \cdot10\$. The voltage slew rate also increases \$dV/dt=I/C\$ just when the Zener conducts. But increasing current x10 also increases R4 power \$(I^2R)\cdot100\$, so the designer forgot to include this in calculations.

This topology has poor characteristics for line voltage and should be avoided.

Replacing R4 with an ICL can prevent inrush currents but is still very inefficient.

An SCR regulator or better a buck forward or flyback regulator is best.

Consider what happens when you increase \$Vin \cdot10\$. The voltage slew rate also increases \$dV/dt=I/C\$ just when the Zener conducts. But increasing current x10 also increases R4 power \$(I^2R)\cdot100\$, so the designer forgot to include this in calculations.

This topology has poor characteristics for line voltage and should be avoided.

Replacing R4 with an ICL can prevent inrush currents but is still very inefficient.

An SCR regulator or better a buck forward or flyback regulator is best.

Even better is ZVS offline regulator with active PFC!

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D.A.S.
  • 148.1k
  • 3
  • 56
  • 190

Consider what happens when you increase \$Vin \cdot10\$. The voltage slew rate also increases \$dV/dt=I/C\$ just when the Zener conducts. But increasing current x10 also increases R4 power \$(I^2R)\cdot100\$, so the designer forgot to include this in calculations.

This topology has poor characteristics for line voltage and should be avoided.

Replacing R4 with an ICL can prevent inrush currents but is still very inefficient.

An SCR regulator or better a buck forward or flyback regulator is best.

Consider what happens when you increase \$Vin \cdot10\$. The voltage slew rate also increases \$dV/dt=I/C\$ just when the Zener conducts. But increasing current x10 also increases R4 power \$(I^2R)\cdot100\$, so the designer forgot to include this in calculations.

Consider what happens when you increase \$Vin \cdot10\$. The voltage slew rate also increases \$dV/dt=I/C\$ just when the Zener conducts. But increasing current x10 also increases R4 power \$(I^2R)\cdot100\$, so the designer forgot to include this in calculations.

This topology has poor characteristics for line voltage and should be avoided.

Replacing R4 with an ICL can prevent inrush currents but is still very inefficient.

An SCR regulator or better a buck forward or flyback regulator is best.

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user105652
user105652

Consider what happens when you increase Vin x10\$Vin \cdot10\$. The voltage slew rate also increases dV/dt=I/C\$dV/dt=I/C\$ just when the Zener conducts. But increasing current x10 also increases R4 power (I^2R) x100\$(I^2R)\cdot100\$, so the designer forgot to include this in calculations.

Consider what happens when you increase Vin x10. The voltage slew rate also increases dV/dt=I/C just when the Zener conducts. But increasing current x10 also increases R4 power (I^2R) x100, so the designer forgot to include this in calculations.

Consider what happens when you increase \$Vin \cdot10\$. The voltage slew rate also increases \$dV/dt=I/C\$ just when the Zener conducts. But increasing current x10 also increases R4 power \$(I^2R)\cdot100\$, so the designer forgot to include this in calculations.

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D.A.S.
  • 148.1k
  • 3
  • 56
  • 190
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