Timeline for Using only stray capacitance for MCU oscillator circuits
Current License: CC BY-SA 4.0
13 events
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| May 2, 2019 at 14:14 | history | edited | analogsystemsrf | CC BY-SA 4.0 |
added 270 characters in body
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| May 2, 2019 at 14:01 | comment | added | analogsystemsrf | I've given you some guidelines for jitter. What other problems should be modeled? | |
| May 2, 2019 at 13:29 | comment | added | mablem8 | @analogsystemsrf I'd gladly accept answers elucidating any of the following! Analytical or quantitative failure modes w/o C_Lx, a process comparable to the AN2867 excerpts to design the circuit using only C_S or when C_L<C_S, a theory-based description of the differences w/ and w/o C_Lx (should be straightforward if Fig 5 is to be taken literally - C_S is in parallel with Q while C_Lx are in series), a non-rule-of-thumb method to determine C_S, or a method parameterized by C_L to quantify phase noise w/ and w/o C_Lx. I may be asking this in the wrong place since math type isn't supported here. | |
| May 2, 2019 at 2:18 | comment | added | analogsystemsrf | What readily-accessible theory(ies) are we needing? oscillator modeling --- linear and transient --- is a trusted skill. If you use the OHMS_LAW for jitter: Tj = Vnoise/Slewrate, then that area becomes clearer. Is the substrate trash the problem? | |
| May 1, 2019 at 17:51 | comment | added | mablem8 | @MichaelKaras Yes, but there may be enough stray capacitance without increasing trace length. It seems that a fundamental problem here is that there is no readily-accessible theory to fall back on in regimes where the rule of thumb breaks down. Good point about using caps to make later adjustments easier. | |
| May 1, 2019 at 16:44 | comment | added | Michael Karas | Let me add here that it has always been best practice to keep the traces to the crystal as short as possible and with as minimal loop cross sectional area as possible. Adding trace to increase stray capacitance flies directly into the face of that. So do not do it. 0402 caps are extremely small and add much more flexibility in adjustment of the circuit after board build. | |
| May 1, 2019 at 16:36 | comment | added | analogsystemsrf | The oscillator's PI network will have slow edges, perhaps 1 volt in 100 nanoseconds. A charge injection of 0.1 volt will cause 10 nanoseconds jitter. Is that a tolerable amount of clock edge jitter? | |
| May 1, 2019 at 15:29 | comment | added | analogsystemsrf | One might indeed proceed to design 2pF or 5pF or 18pF capacitors into the copper foils. The areas involved make the "parasitic capacitors" very vulnerable to Efield aggressors which, again, increases the injected non-synchronous energy and thus boosts the (deterministic) jitter (phasenoise). | |
| May 1, 2019 at 13:19 | comment | added | mablem8 | @analogsystemsrf Thanks for addressing the MCU side of the circuit! The downvote is not mine. The question remains unanswered - if an oscillator requiring a 2pF - 5pF load capacitance is used in a design, is there any problem depending on the stray capacitance only? It's not clear why that would result in higher phase noise. It seems like clever (or maybe even not-so-clever) use of traces could eliminate the need for two components from the design. | |
| May 1, 2019 at 6:18 | comment | added | Glenn Willen | I expect that this answer was downvoted (not by me!) because (1) it is kind of hard to understand (what's phase noise? what's 'MCU trash' supposed to mean? What's a "PI network"? I know the answers to some of these questions, but they're not going to be obvious to the questioner necessarily without being explained.) And (2) it uses boldface and capital letters in quirky ways, which comes across as kind of aggressive. | |
| May 1, 2019 at 6:14 | comment | added | Unknown123 | Why the downvote? | |
| May 1, 2019 at 6:11 | comment | added | analogsystemsrf | This answer is precisely addressing the question at the end of OP's text. | |
| May 1, 2019 at 5:56 | history | answered | analogsystemsrf | CC BY-SA 4.0 |