Timeline for drawing a circuit, nand gates
Current License: CC BY-SA 4.0
6 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| May 3, 2019 at 21:06 | comment | added | D.A.S. | so you now see the light of logic, now there are only a couple more rules, then methods to design it, good logic but for language there are 144 rules of bad logic defined by Aristotle and Plato. ha. ( called fallacies ) Language and Black's Law (for legal) still use these fundamental de Morgan's Laws for language | |
| May 3, 2019 at 20:09 | vote | accept | lightsodium | ||
| May 3, 2019 at 20:09 | comment | added | lightsodium | I finally understood it! Thanks a lot. | |
| May 3, 2019 at 19:33 | comment | added | D.A.S. | Yes inverting both inputs and outputs results in switching inputs NAND to OR which is not what you want. So do you understand that you must use De Morgan's Law to test your understanding is wrong and that the solution requires inverting each NAND ( due to restriction in question) | |
| May 3, 2019 at 18:54 | comment | added | lightsodium | I think I understand it by time. How do you get the AND gates, which the arrow shows to? I just understand that the OR gate comes from not (abcd) which is according to DeMorgan's Theorem not (ab) + not (cd). Edit: Do you want to show with the AND gates that they are only inverted? | |
| May 3, 2019 at 18:22 | history | answered | D.A.S. | CC BY-SA 4.0 |