Skip to main content
6 events
when toggle format what by license comment
May 5, 2019 at 15:16 comment added James G-J Thank you for all the advice, Sunnyskyguy. I plan on getting proper PCBs made for the final installation of this system (which will include more than 10x the number of solenoids) - however I was crunched for time when installing this smaller test version and so I went with what I knew, perfboard. I appreciate your help!
May 5, 2019 at 15:05 comment added D.A.S. Also in future make a PCB and find a cheap board shop for $50 prototypes. Consider all wire output inductance to reduce stray coupling from input to output. Put a snubber RF cap on CLK & data to avoid false data if necessary 100 pF... or use twisted pairs. CM clamp choke on solenoid wire bundle reduces noise > 1MHz if necessary.
May 5, 2019 at 14:46 comment added James G-J Great, thank you for the insight! Unfortunately, I'm away from the hardware and will not be able to make these changes for another week - once I return I will try this and be able to accept your answer, I appreciate your patience.
May 5, 2019 at 14:39 comment added D.A.S. 0.1 ceramic near each CMOS IC. 10uF to 100uF Tantalum or low ESR Alum cap near 12V input such that the 5V logic ground does not share ground current from solenoids
May 5, 2019 at 14:29 comment added James G-J Thanks for the response. I do have all grounds tied together on the board (I think). Could you please be more clear as to where these e-caps should be added, and perhaps an estimate to their value?
May 5, 2019 at 14:22 history answered D.A.S. CC BY-SA 4.0