Timeline for Simple counter circuit resets at the wrong value
Current License: CC BY-SA 4.0
12 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| May 8, 2019 at 9:11 | vote | accept | cdummie | ||
| May 7, 2019 at 19:43 | comment | added | jonk | @cdummie Okay. I think I got my errors fixed up. But do check on my logic. | |
| May 7, 2019 at 19:25 | answer | added | jonk | timeline score: 1 | |
| May 7, 2019 at 18:59 | comment | added | jonk | @cdummie Okay. I'll write up something. | |
| May 7, 2019 at 18:55 | comment | added | cdummie | @jonk I've heard of it, but i am not quite sure what it is | |
| May 7, 2019 at 18:51 | comment | added | jonk | @cdummie It's how you have your JK's wired. Just a "toggle" FF. Have you ever heard of an excitation table? | |
| May 7, 2019 at 18:48 | comment | added | cdummie | @jonk What is TFF? | |
| May 7, 2019 at 18:34 | comment | added | jonk | @cdummie Just prepare an excitation table for your TFF-wired JKs. Have you done that? | |
| May 7, 2019 at 18:03 | comment | added | cdummie | @Oldfart Thank you for your response, if i understood you well, you are saying that reset pulse is removed right after one of the flip flops changes it's state. But if that's the case, how come that reseting to 2 still happens, it just happens earlier than it should? | |
| May 7, 2019 at 13:22 | comment | added | Oldfart | You are doing an asynchronous set/reset based on the current state. That is inherent unreliable: the reset pulse itself is removed as soon as one of the register output changes. In fact you are making a reset spike. | |
| May 7, 2019 at 11:42 | history | edited | SamGibson♦ | CC BY-SA 4.0 |
Grammar changes to improve readability.
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| May 7, 2019 at 10:24 | history | asked | cdummie | CC BY-SA 4.0 |