Timeline for VHDL: What is correct way to model open collector output for FPGA?
Current License: CC BY-SA 4.0
9 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jul 23, 2021 at 0:17 | vote | accept | quantum231 | ||
| Jun 14, 2019 at 8:04 | answer | added | Dmitry Grigoryev | timeline score: 6 | |
| Jun 14, 2019 at 5:00 | comment | added | quantum231 | The main difficulty is simulation side of this | |
| Jun 14, 2019 at 4:43 | history | became hot network question | |||
| Jun 14, 2019 at 0:00 | history | tweeted | twitter.com/StackElectronix/status/1139321600841539584 | ||
| Jun 13, 2019 at 20:43 | answer | added | user103380 | timeline score: 7 | |
| Jun 13, 2019 at 20:40 | answer | added | Grabul | timeline score: 12 | |
| Jun 13, 2019 at 20:34 | comment | added | Eugene Sh. | intel.com/content/www/us/en/programmable/support/… | |
| Jun 13, 2019 at 20:31 | history | asked | quantum231 | CC BY-SA 4.0 |