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I don't think it matters. Synthesis will smash this down to 136 2:1 muxes regardless of how you describe them in HDL. That's not that much in the larger scheme of things if you're building something with that large of a datapath (128 data, 8 enables?) Insert register slices if you need help to close timing.

I don't think it matters. Synthesis will smash this down to 136 2:1 muxes regardless of how you describe them in HDL. That's not that much in the larger scheme of things if you're building something with that large of a datapath (128 data, 8 enables, right?) 

Insert register slices if it needs help to close timing.

I don't think it matters. Synthesis will smash this down to 136 2:1 muxes regardless of how you describe them in HDL. That's not that much in the larger scheme of things if you're building something with that large of a datapath (128 data, 8 enables?) Insert a register slice if you need to.

I don't think it matters. Synthesis will smash this down to 136 2:1 muxes regardless of how you describe them in HDL. That's not that much in the larger scheme of things if you're building something with that large of a datapath (128 data, 8 enables?) Insert register slices if you need help to close timing.

I don't think it matters. Synthesis will smash this down to 136 2:1 muxes regardless of how you describe them in HDL. That's not that much in the larger scheme of things if you're building something with that large of a datapath (128 data, 8 enables?)

I don't think it matters. Synthesis will smash this down to 136 2:1 muxes regardless of how you describe them in HDL. That's not that much in the larger scheme of things if you're building something with that large of a datapath (128 data, 8 enables?) Insert a register slice if you need to.