Timeline for RS422 Receiver Not Reporting Errors When Too Few Stop Bits
Current License: CC BY-SA 4.0
2 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Aug 21, 2019 at 22:59 | comment | added | Christian B. | Well two stop bits make sure that even for drifting clocks sender and receiver are "on the same page" i.e. even if their clocks diverge the two clock cycles make sure that both have enough time to reach the "resting" state. Especially if one uses the far from perfect internal oscillators and high baud rates. So I would disagree with the claim that it is just a remnant. | |
| Aug 21, 2019 at 22:36 | history | answered | TimWescott | CC BY-SA 4.0 |