Timeline for State Diagram with two inputs
Current License: CC BY-SA 4.0
12 events
| when toggle format | what | by | license | comment | |
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| Sep 14, 2019 at 0:05 | review | First posts | |||
| Sep 14, 2019 at 12:43 | |||||
| Sep 9, 2019 at 9:36 | vote | accept | George Beatle | ||
| Sep 9, 2019 at 0:05 | answer | added | StainlessSteelRat | timeline score: 1 | |
| Sep 8, 2019 at 14:54 | comment | added | Elliot Alderson | Well, the truth table looks like it does not agree with the state diagram. Your truth table shows two transitions from state 00 to state 10 but your state diagram shows just one transition from 00 to 10. Also, "is this right?" is not the kind of question we usually answer here...I think you will need to do a lot more work yourself before we can help you. | |
| Sep 8, 2019 at 14:29 | history | edited | George Beatle | CC BY-SA 4.0 |
added 89 characters in body
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| Sep 8, 2019 at 14:28 | comment | added | George Beatle | thank you very much for your previous advice. I have done the truth table of the problem. Is this right? | |
| Sep 8, 2019 at 13:10 | review | Close votes | |||
| Sep 26, 2019 at 15:22 | |||||
| Sep 8, 2019 at 13:02 | comment | added | Elliot Alderson | Why don't you try writing a state table. Make a table that shows, for every possible combination of values of A, B, and the current state, what the next state and output value should be. You have two state bits (plus A and B) so it looks like you need at total of 16 rows in the table. | |
| Sep 8, 2019 at 12:58 | comment | added | George Beatle | I mean that if A: 1 1 1 0 1 0 1 0 and B: 1 0 1 0 1 1 1 0 then output would be Y: 0 1 0 0 0 0 1 1. I certainly do not want the solution. I just kindly request if my above state diagram is right? Do I misunderstand something? Because I know how to make state diagram. But this seems something new to me. That's why, if you could help me... | |
| Sep 8, 2019 at 12:57 | comment | added | George Beatle | yes exit is the output and let me rephrase the "reverse sentence". Initially the output Y is set to 1 when the values of A and B are different and to 0 when they are the same. When the circuit detects that three consecutive samples of A and B have the same value then (from the next clock pulse) or output Y is set to 1 when the values A and B are the same and to 0 when they are different. | |
| Sep 8, 2019 at 12:51 | comment | added | Elliot Alderson | When someone asks for help with a homework problem we expect them to show a significant amount of effort to solve the problem themselves and to ask a specific question. Your description is also a bit confusing...by "exit" do you mean "output"? What does "exit will reverse" mean? | |
| Sep 8, 2019 at 10:27 | history | asked | George Beatle | CC BY-SA 4.0 |