Timeline for Verilog Code for this (simple) Logic Gate?
Current License: CC BY-SA 4.0
2 events
when toggle format | what | by | license | comment | |
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Sep 13, 2019 at 3:04 | comment | added | user39382 | I get the sense that this exercise is intended to demonstrate to the student how structural Verilog can get clunky when used this way. :) | |
Sep 13, 2019 at 0:55 | history | answered | hacktastical | CC BY-SA 4.0 |