Timeline for P channel mosfet as a switch on logic level
Current License: CC BY-SA 4.0
3 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Oct 3, 2019 at 18:43 | answer | added | Spehro 'speff' Pefhany | timeline score: 1 | |
| Oct 3, 2019 at 18:06 | comment | added | The Photon | Your sources and drains are reversed. Source connects to power, drain connects to load, just like with an NMOS on the low side. As drawn, your loads will constantly receive power through the body diodes of your FETs. | |
| Oct 3, 2019 at 18:03 | history | asked | Oxmaster | CC BY-SA 4.0 |