Timeline for Differential to single ended digital signal
Current License: CC BY-SA 4.0
6 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Oct 18, 2019 at 23:00 | comment | added | Emerald | this is on silicon wafer ........... | |
| Oct 18, 2019 at 0:19 | comment | added | Marcus Müller | "I have a 8 GHz differential clock": In which shape? Freespace RF wave? Balanced coax? Coplanar microstrip line? Twinax? very short unmatched distance on PCB? On silicon wafer? | |
| Oct 17, 2019 at 21:52 | answer | added | D.A.S. | timeline score: 1 | |
| Oct 17, 2019 at 21:34 | comment | added | DKNguyen | I would think that clock is differential for a reason, especially at 8GHz. I would do everything I could to keep it that way. You also probably can't take just one end and ignore the other since it's probably some exotic high-speed signalling level. Don't cut corners at 8GHz. | |
| Oct 17, 2019 at 21:20 | review | First posts | |||
| Oct 18, 2019 at 0:27 | |||||
| Oct 17, 2019 at 21:17 | history | asked | Emerald | CC BY-SA 4.0 |